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-rwxr-xr-xpart_3/ex11/.qsys_edit/filters.xml4
-rwxr-xr-xpart_3/ex11/.qsys_edit/preferences.xml24
-rw-r--r--part_3/ex11/db/_cmp.kptbin700 -> 0 bytes
-rwxr-xr-xpart_3/ex11/ex10.v.bak2
-rwxr-xr-xpart_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do34
-rwxr-xr-xpart_3/ex11/simulation/modelsim/rtl_work/_info50
-rwxr-xr-xpart_3/ex11/simulation/modelsim/rtl_work/_vmake6
-rwxr-xr-xpart_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd60
8 files changed, 90 insertions, 90 deletions
diff --git a/part_3/ex11/.qsys_edit/filters.xml b/part_3/ex11/.qsys_edit/filters.xml
index 25484e0..2c6ab93 100755
--- a/part_3/ex11/.qsys_edit/filters.xml
+++ b/part_3/ex11/.qsys_edit/filters.xml
@@ -1,2 +1,2 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<filters version="16.0" />
+<?xml version="1.0" encoding="UTF-8"?>
+<filters version="16.0" />
diff --git a/part_3/ex11/.qsys_edit/preferences.xml b/part_3/ex11/.qsys_edit/preferences.xml
index ea0fb24..c5b7680 100755
--- a/part_3/ex11/.qsys_edit/preferences.xml
+++ b/part_3/ex11/.qsys_edit/preferences.xml
@@ -1,12 +1,12 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<preferences>
- <debug showDebugMenu="0" />
- <systemtable filter="All Interfaces">
- <columns>
- <connections preferredWidth="47" />
- <irq preferredWidth="34" />
- </columns>
- </systemtable>
- <library expandedCategories="Project,Library" />
- <window width="1100" height="800" x="0" y="0" />
-</preferences>
+<?xml version="1.0" encoding="UTF-8"?>
+<preferences>
+ <debug showDebugMenu="0" />
+ <systemtable filter="All Interfaces">
+ <columns>
+ <connections preferredWidth="47" />
+ <irq preferredWidth="34" />
+ </columns>
+ </systemtable>
+ <library expandedCategories="Project,Library" />
+ <window width="1100" height="800" x="0" y="0" />
+</preferences>
diff --git a/part_3/ex11/db/_cmp.kpt b/part_3/ex11/db/_cmp.kpt
deleted file mode 100644
index bd9e7c9..0000000
--- a/part_3/ex11/db/_cmp.kpt
+++ /dev/null
Binary files differ
diff --git a/part_3/ex11/ex10.v.bak b/part_3/ex11/ex10.v.bak
index d3f5a12..8b13789 100755
--- a/part_3/ex11/ex10.v.bak
+++ b/part_3/ex11/ex10.v.bak
@@ -1 +1 @@
-
+
diff --git a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
index 52dd5a2..b12a7d7 100755
--- a/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
+++ b/part_3/ex11/simulation/modelsim/do_files/tb_spi2dac.do
@@ -1,17 +1,17 @@
-add wave -position end sysclk
-add wave -position end -hexadecimal data_in
-add wave -position end load
-add wave -position end dac_sdi
-add wave -position end dac_cs
-add wave -position end dac_sck
-add wave -position end dac_ld
-force sysclk 1 0, 0 10ns -r 20ns
-force data_in 10'h23b
-force load 0
-run 200ns
-force load 1
-run 400ns
-force load 0
-run 20us
-
-
+add wave -position end sysclk
+add wave -position end -hexadecimal data_in
+add wave -position end load
+add wave -position end dac_sdi
+add wave -position end dac_cs
+add wave -position end dac_sck
+add wave -position end dac_ld
+force sysclk 1 0, 0 10ns -r 20ns
+force data_in 10'h23b
+force load 0
+run 200ns
+force load 1
+run 400ns
+force load 0
+run 20us
+
+
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_info b/part_3/ex11/simulation/modelsim/rtl_work/_info
index 63648ac..499bdd4 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_info
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_info
@@ -1,25 +1,25 @@
-m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255
+K3
+13
+cModel Technology
+Z0 dC:\New folder\ex10\simulation\modelsim
+vspi2dac
+!i10b 1
+!s100 Yc_:?1WP<4LKj7cQXiUbl1
+IzTNjHgWKkeSFYc0]WM5Gm2
+VFNOGDa=aYhJTn=76LYB@A2
+Z1 dC:\New folder\ex10\simulation\modelsim
+w1478805578
+8C:/New folder/ex10/verilog_files/spi2dac.v
+FC:/New folder/ex10/verilog_files/spi2dac.v
+L0 9
+OV;L;10.1d;51
+r1
+!s85 0
+31
+!s108 1480413939.783000
+!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
+!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
+!s101 -O0
+o-vlog01compat -work work -O0
+!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/_vmake b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
index b51b305..2f7e729 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/_vmake
+++ b/part_3/ex11/simulation/modelsim/rtl_work/_vmake
@@ -1,3 +1,3 @@
-m255
-K3
-cModel Technology
+m255
+K3
+cModel Technology
diff --git a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
index 2a503c0..e874ed3 100755
--- a/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
+++ b/part_3/ex11/simulation/modelsim/rtl_work/spi2dac/_primary.vhd
@@ -1,30 +1,30 @@
-library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
- generic(
- BUF : vl_logic := Hi1;
- GA_N : vl_logic := Hi1;
- SHDN_N : vl_logic := Hi1;
- TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
- IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
- WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1);
- WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0)
- );
- port(
- sysclk : in vl_logic;
- data_in : in vl_logic_vector(9 downto 0);
- load : in vl_logic;
- dac_sdi : out vl_logic;
- dac_cs : out vl_logic;
- dac_sck : out vl_logic;
- dac_ld : out vl_logic
- );
- attribute mti_svvh_generic_type : integer;
- attribute mti_svvh_generic_type of BUF : constant is 1;
- attribute mti_svvh_generic_type of GA_N : constant is 1;
- attribute mti_svvh_generic_type of SHDN_N : constant is 1;
- attribute mti_svvh_generic_type of TC : constant is 1;
- attribute mti_svvh_generic_type of IDLE : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog;
+use verilog.vl_types.all;
+entity spi2dac is
+ generic(
+ BUF : vl_logic := Hi1;
+ GA_N : vl_logic := Hi1;
+ SHDN_N : vl_logic := Hi1;
+ TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
+ IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
+ WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1);
+ WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0)
+ );
+ port(
+ sysclk : in vl_logic;
+ data_in : in vl_logic_vector(9 downto 0);
+ load : in vl_logic;
+ dac_sdi : out vl_logic;
+ dac_cs : out vl_logic;
+ dac_sck : out vl_logic;
+ dac_ld : out vl_logic
+ );
+ attribute mti_svvh_generic_type : integer;
+ attribute mti_svvh_generic_type of BUF : constant is 1;
+ attribute mti_svvh_generic_type of GA_N : constant is 1;
+ attribute mti_svvh_generic_type of SHDN_N : constant is 1;
+ attribute mti_svvh_generic_type of TC : constant is 1;
+ attribute mti_svvh_generic_type of IDLE : constant is 1;
+ attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
+ attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
+end spi2dac;
generated by cgit (git 2.34.1) at 2024-07-05 11:16:03 +0000