diff options
Diffstat (limited to 'part_3/ex13/simulation/modelsim/rtl_work')
-rwxr-xr-x | part_3/ex13/simulation/modelsim/rtl_work/_info | 50 | ||||
-rwxr-xr-x | part_3/ex13/simulation/modelsim/rtl_work/_vmake | 6 | ||||
-rwxr-xr-x | part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd | 60 |
3 files changed, 58 insertions, 58 deletions
diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_info b/part_3/ex13/simulation/modelsim/rtl_work/_info index 63648ac..499bdd4 100755 --- a/part_3/ex13/simulation/modelsim/rtl_work/_info +++ b/part_3/ex13/simulation/modelsim/rtl_work/_info @@ -1,25 +1,25 @@ -m255
-K3
-13
-cModel Technology
-Z0 dC:\New folder\ex10\simulation\modelsim
-vspi2dac
-!i10b 1
-!s100 Yc_:?1WP<4LKj7cQXiUbl1
-IzTNjHgWKkeSFYc0]WM5Gm2
-VFNOGDa=aYhJTn=76LYB@A2
-Z1 dC:\New folder\ex10\simulation\modelsim
-w1478805578
-8C:/New folder/ex10/verilog_files/spi2dac.v
-FC:/New folder/ex10/verilog_files/spi2dac.v
-L0 9
-OV;L;10.1d;51
-r1
-!s85 0
-31
-!s108 1480413939.783000
-!s107 C:/New folder/ex10/verilog_files/spi2dac.v|
-!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v|
-!s101 -O0
-o-vlog01compat -work work -O0
-!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0
+m255 +K3 +13 +cModel Technology +Z0 dC:\New folder\ex10\simulation\modelsim +vspi2dac +!i10b 1 +!s100 Yc_:?1WP<4LKj7cQXiUbl1 +IzTNjHgWKkeSFYc0]WM5Gm2 +VFNOGDa=aYhJTn=76LYB@A2 +Z1 dC:\New folder\ex10\simulation\modelsim +w1478805578 +8C:/New folder/ex10/verilog_files/spi2dac.v +FC:/New folder/ex10/verilog_files/spi2dac.v +L0 9 +OV;L;10.1d;51 +r1 +!s85 0 +31 +!s108 1480413939.783000 +!s107 C:/New folder/ex10/verilog_files/spi2dac.v| +!s90 -reportprogress|300|-vlog01compat|-work|work|+incdir+C:/New folder/ex10/verilog_files|C:/New folder/ex10/verilog_files/spi2dac.v| +!s101 -O0 +o-vlog01compat -work work -O0 +!s92 -vlog01compat -work work {+incdir+C:/New folder/ex10/verilog_files} -O0 diff --git a/part_3/ex13/simulation/modelsim/rtl_work/_vmake b/part_3/ex13/simulation/modelsim/rtl_work/_vmake index b51b305..2f7e729 100755 --- a/part_3/ex13/simulation/modelsim/rtl_work/_vmake +++ b/part_3/ex13/simulation/modelsim/rtl_work/_vmake @@ -1,3 +1,3 @@ -m255
-K3
-cModel Technology
+m255 +K3 +cModel Technology diff --git a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd index 2a503c0..e874ed3 100755 --- a/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd +++ b/part_3/ex13/simulation/modelsim/rtl_work/spi2dac/_primary.vhd @@ -1,30 +1,30 @@ -library verilog;
-use verilog.vl_types.all;
-entity spi2dac is
- generic(
- BUF : vl_logic := Hi1;
- GA_N : vl_logic := Hi1;
- SHDN_N : vl_logic := Hi1;
- TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0);
- IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0);
- WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1);
- WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0)
- );
- port(
- sysclk : in vl_logic;
- data_in : in vl_logic_vector(9 downto 0);
- load : in vl_logic;
- dac_sdi : out vl_logic;
- dac_cs : out vl_logic;
- dac_sck : out vl_logic;
- dac_ld : out vl_logic
- );
- attribute mti_svvh_generic_type : integer;
- attribute mti_svvh_generic_type of BUF : constant is 1;
- attribute mti_svvh_generic_type of GA_N : constant is 1;
- attribute mti_svvh_generic_type of SHDN_N : constant is 1;
- attribute mti_svvh_generic_type of TC : constant is 1;
- attribute mti_svvh_generic_type of IDLE : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1;
- attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1;
-end spi2dac;
+library verilog; +use verilog.vl_types.all; +entity spi2dac is + generic( + BUF : vl_logic := Hi1; + GA_N : vl_logic := Hi1; + SHDN_N : vl_logic := Hi1; + TC : vl_logic_vector(0 to 4) := (Hi1, Hi1, Hi0, Hi0, Hi0); + IDLE : vl_logic_vector(0 to 1) := (Hi0, Hi0); + WAIT_CSB_FALL : vl_logic_vector(0 to 1) := (Hi0, Hi1); + WAIT_CSB_HIGH : vl_logic_vector(0 to 1) := (Hi1, Hi0) + ); + port( + sysclk : in vl_logic; + data_in : in vl_logic_vector(9 downto 0); + load : in vl_logic; + dac_sdi : out vl_logic; + dac_cs : out vl_logic; + dac_sck : out vl_logic; + dac_ld : out vl_logic + ); + attribute mti_svvh_generic_type : integer; + attribute mti_svvh_generic_type of BUF : constant is 1; + attribute mti_svvh_generic_type of GA_N : constant is 1; + attribute mti_svvh_generic_type of SHDN_N : constant is 1; + attribute mti_svvh_generic_type of TC : constant is 1; + attribute mti_svvh_generic_type of IDLE : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_FALL : constant is 1; + attribute mti_svvh_generic_type of WAIT_CSB_HIGH : constant is 1; +end spi2dac; |