1 files changed, 447 insertions, 0 deletions

diff --git a/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf b/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf
new file mode 100755
index 0000000..491bf63
--- /dev/null
+++ b/part_3/ex14/simulation/modelsim/ex10_modelsim.xrf
@@ -0,0 +1,447 @@
+vendor_name = ModelSim

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/add3_ge5.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/hex_to_7seg.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/bin2bcd_16.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/ex14.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.qip

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/ROM.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/tick_5000.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/spi2dac.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/verilog_files/pwm.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.qip

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/const_mult.v

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/add_offset.v

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/stratix_ram_block.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mux.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_decode.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/aglobal160.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/a_rdenreg.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altrom.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altram.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altdpram.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/cbx.lst

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/altsyncram_6ng1.tdf

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/rom_data/rom_data.mif

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/bypassff.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/csa_add.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/muleabz.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_lfrg.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mul_boothc.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_ded_mult_y.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/dffpipe.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/addcore.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/look_add.inc

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/alt_stratix_add_sub.inc

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_d9h.tdf

+source_file = 1, //icnas3.cc.ic.ac.uk/ml7715/Desktop/ex14/db/add_sub_89h.tdf

+source_file = 1, c:/altera/16.0/quartus/libraries/megafunctions/altshift.tdf

+design_name = ex14

+instance = comp, \DAC_CS~output , DAC_CS~output, ex14, 1

+instance = comp, \DAC_SDI~output , DAC_SDI~output, ex14, 1

+instance = comp, \DAC_LD~output , DAC_LD~output, ex14, 1

+instance = comp, \DAC_SCK~output , DAC_SCK~output, ex14, 1

+instance = comp, \PWM_OUT~output , PWM_OUT~output, ex14, 1

+instance = comp, \HEX0[0]~output , HEX0[0]~output, ex14, 1

+instance = comp, \HEX0[1]~output , HEX0[1]~output, ex14, 1

+instance = comp, \HEX0[2]~output , HEX0[2]~output, ex14, 1

+instance = comp, \HEX0[3]~output , HEX0[3]~output, ex14, 1

+instance = comp, \HEX0[4]~output , HEX0[4]~output, ex14, 1

+instance = comp, \HEX0[5]~output , HEX0[5]~output, ex14, 1

+instance = comp, \HEX0[6]~output , HEX0[6]~output, ex14, 1

+instance = comp, \HEX1[0]~output , HEX1[0]~output, ex14, 1

+instance = comp, \HEX1[1]~output , HEX1[1]~output, ex14, 1

+instance = comp, \HEX1[2]~output , HEX1[2]~output, ex14, 1

+instance = comp, \HEX1[3]~output , HEX1[3]~output, ex14, 1

+instance = comp, \HEX1[4]~output , HEX1[4]~output, ex14, 1

+instance = comp, \HEX1[5]~output , HEX1[5]~output, ex14, 1

+instance = comp, \HEX1[6]~output , HEX1[6]~output, ex14, 1

+instance = comp, \HEX2[0]~output , HEX2[0]~output, ex14, 1

+instance = comp, \HEX2[1]~output , HEX2[1]~output, ex14, 1

+instance = comp, \HEX2[2]~output , HEX2[2]~output, ex14, 1

+instance = comp, \HEX2[3]~output , HEX2[3]~output, ex14, 1

+instance = comp, \HEX2[4]~output , HEX2[4]~output, ex14, 1

+instance = comp, \HEX2[5]~output , HEX2[5]~output, ex14, 1

+instance = comp, \HEX2[6]~output , HEX2[6]~output, ex14, 1

+instance = comp, \HEX3[0]~output , HEX3[0]~output, ex14, 1

+instance = comp, \HEX3[1]~output , HEX3[1]~output, ex14, 1

+instance = comp, \HEX3[2]~output , HEX3[2]~output, ex14, 1

+instance = comp, \HEX3[3]~output , HEX3[3]~output, ex14, 1

+instance = comp, \HEX3[4]~output , HEX3[4]~output, ex14, 1

+instance = comp, \HEX3[5]~output , HEX3[5]~output, ex14, 1

+instance = comp, \HEX3[6]~output , HEX3[6]~output, ex14, 1

+instance = comp, \HEX4[0]~output , HEX4[0]~output, ex14, 1

+instance = comp, \HEX4[1]~output , HEX4[1]~output, ex14, 1

+instance = comp, \HEX4[2]~output , HEX4[2]~output, ex14, 1

+instance = comp, \HEX4[3]~output , HEX4[3]~output, ex14, 1

+instance = comp, \HEX4[4]~output , HEX4[4]~output, ex14, 1

+instance = comp, \HEX4[5]~output , HEX4[5]~output, ex14, 1

+instance = comp, \HEX4[6]~output , HEX4[6]~output, ex14, 1

+instance = comp, \CLOCK_50~input , CLOCK_50~input, ex14, 1

+instance = comp, \CLOCK_50~inputCLKENA0 , CLOCK_50~inputCLKENA0, ex14, 1

+instance = comp, \dac|ctr[2] , dac|ctr[2], ex14, 1

+instance = comp, \dac|ctr~1 , dac|ctr~1, ex14, 1

+instance = comp, \dac|ctr[0] , dac|ctr[0], ex14, 1

+instance = comp, \dac|Add0~1 , dac|Add0~1, ex14, 1

+instance = comp, \dac|ctr[3] , dac|ctr[3], ex14, 1

+instance = comp, \dac|ctr[0]~DUPLICATE , dac|ctr[0]~DUPLICATE, ex14, 1

+instance = comp, \dac|Add0~0 , dac|Add0~0, ex14, 1

+instance = comp, \dac|ctr[4] , dac|ctr[4], ex14, 1

+instance = comp, \dac|ctr[3]~DUPLICATE , dac|ctr[3]~DUPLICATE, ex14, 1

+instance = comp, \dac|ctr~0 , dac|ctr~0, ex14, 1

+instance = comp, \dac|ctr[2]~DUPLICATE , dac|ctr[2]~DUPLICATE, ex14, 1

+instance = comp, \dac|ctr~2 , dac|ctr~2, ex14, 1

+instance = comp, \dac|ctr[1] , dac|ctr[1], ex14, 1

+instance = comp, \dac|clk_1MHz~0 , dac|clk_1MHz~0, ex14, 1

+instance = comp, \dac|clk_1MHz~feeder , dac|clk_1MHz~feeder, ex14, 1

+instance = comp, \dac|clk_1MHz , dac|clk_1MHz, ex14, 1

+instance = comp, \dac|state~0 , dac|state~0, ex14, 1

+instance = comp, \dac|state[4] , dac|state[4], ex14, 1

+instance = comp, \tick|count[15]~DUPLICATE , tick|count[15]~DUPLICATE, ex14, 1

+instance = comp, \tick|Add0~9 , tick|Add0~9, ex14, 1

+instance = comp, \tick|count[0]~1 , tick|count[0]~1, ex14, 1

+instance = comp, \tick|count[0] , tick|count[0], ex14, 1

+instance = comp, \tick|Add0~13 , tick|Add0~13, ex14, 1

+instance = comp, \tick|count[1]~2 , tick|count[1]~2, ex14, 1

+instance = comp, \tick|count[1] , tick|count[1], ex14, 1

+instance = comp, \tick|Add0~17 , tick|Add0~17, ex14, 1

+instance = comp, \tick|count[2]~3 , tick|count[2]~3, ex14, 1

+instance = comp, \tick|count[2] , tick|count[2], ex14, 1

+instance = comp, \tick|Add0~37 , tick|Add0~37, ex14, 1

+instance = comp, \tick|count[3] , tick|count[3], ex14, 1

+instance = comp, \tick|Add0~41 , tick|Add0~41, ex14, 1

+instance = comp, \tick|count[4] , tick|count[4], ex14, 1

+instance = comp, \tick|Add0~45 , tick|Add0~45, ex14, 1

+instance = comp, \tick|count[5]~feeder , tick|count[5]~feeder, ex14, 1

+instance = comp, \tick|count[5]~DUPLICATE , tick|count[5]~DUPLICATE, ex14, 1

+instance = comp, \tick|Add0~5 , tick|Add0~5, ex14, 1

+instance = comp, \tick|count[6] , tick|count[6], ex14, 1

+instance = comp, \tick|Add0~21 , tick|Add0~21, ex14, 1

+instance = comp, \tick|count[7]~4 , tick|count[7]~4, ex14, 1

+instance = comp, \tick|count[7]~DUPLICATE , tick|count[7]~DUPLICATE, ex14, 1

+instance = comp, \tick|Add0~25 , tick|Add0~25, ex14, 1

+instance = comp, \tick|count[8]~5 , tick|count[8]~5, ex14, 1

+instance = comp, \tick|count[8] , tick|count[8], ex14, 1

+instance = comp, \tick|Add0~1 , tick|Add0~1, ex14, 1

+instance = comp, \tick|count[9]~0 , tick|count[9]~0, ex14, 1

+instance = comp, \tick|count[9] , tick|count[9], ex14, 1

+instance = comp, \tick|Add0~49 , tick|Add0~49, ex14, 1

+instance = comp, \tick|count[10] , tick|count[10], ex14, 1

+instance = comp, \tick|Add0~53 , tick|Add0~53, ex14, 1

+instance = comp, \tick|count[11] , tick|count[11], ex14, 1

+instance = comp, \tick|Add0~29 , tick|Add0~29, ex14, 1

+instance = comp, \tick|count[12]~6 , tick|count[12]~6, ex14, 1

+instance = comp, \tick|count[12] , tick|count[12], ex14, 1

+instance = comp, \tick|Add0~57 , tick|Add0~57, ex14, 1

+instance = comp, \tick|count[13] , tick|count[13], ex14, 1

+instance = comp, \tick|Add0~61 , tick|Add0~61, ex14, 1

+instance = comp, \tick|count[14] , tick|count[14], ex14, 1

+instance = comp, \tick|Add0~33 , tick|Add0~33, ex14, 1

+instance = comp, \tick|count[15] , tick|count[15], ex14, 1

+instance = comp, \tick|count[5] , tick|count[5], ex14, 1

+instance = comp, \tick|Equal0~1 , tick|Equal0~1, ex14, 1

+instance = comp, \tick|count[7] , tick|count[7], ex14, 1

+instance = comp, \tick|Equal0~0 , tick|Equal0~0, ex14, 1

+instance = comp, \tick|Equal0~2 , tick|Equal0~2, ex14, 1

+instance = comp, \tick|Equal0~3 , tick|Equal0~3, ex14, 1

+instance = comp, \tick|CLK_OUT~feeder , tick|CLK_OUT~feeder, ex14, 1

+instance = comp, \tick|CLK_OUT , tick|CLK_OUT, ex14, 1

+instance = comp, \dac|sr_state.IDLE~0 , dac|sr_state.IDLE~0, ex14, 1

+instance = comp, \dac|sr_state.IDLE , dac|sr_state.IDLE, ex14, 1

+instance = comp, \dac|Selector2~0 , dac|Selector2~0, ex14, 1

+instance = comp, \dac|sr_state.WAIT_CSB_HIGH , dac|sr_state.WAIT_CSB_HIGH, ex14, 1

+instance = comp, \dac|sr_state.WAIT_CSB_FALL~0 , dac|sr_state.WAIT_CSB_FALL~0, ex14, 1

+instance = comp, \dac|sr_state.WAIT_CSB_FALL , dac|sr_state.WAIT_CSB_FALL, ex14, 1

+instance = comp, \dac|Selector3~0 , dac|Selector3~0, ex14, 1

+instance = comp, \dac|state[0] , dac|state[0], ex14, 1

+instance = comp, \dac|state~2 , dac|state~2, ex14, 1

+instance = comp, \dac|state[2] , dac|state[2], ex14, 1

+instance = comp, \dac|state[3] , dac|state[3], ex14, 1

+instance = comp, \dac|state~3 , dac|state~3, ex14, 1

+instance = comp, \dac|state[3]~DUPLICATE , dac|state[3]~DUPLICATE, ex14, 1

+instance = comp, \dac|state~1 , dac|state~1, ex14, 1

+instance = comp, \dac|state[1] , dac|state[1], ex14, 1

+instance = comp, \dac|WideNor0 , dac|WideNor0, ex14, 1

+instance = comp, \SW[0]~input , SW[0]~input, ex14, 1

+instance = comp, \fin_address|Add0~1 , fin_address|Add0~1, ex14, 1

+instance = comp, \fin_address|address[0] , fin_address|address[0], ex14, 1

+instance = comp, \SW[1]~input , SW[1]~input, ex14, 1

+instance = comp, \fin_address|Add0~5 , fin_address|Add0~5, ex14, 1

+instance = comp, \fin_address|address[1] , fin_address|address[1], ex14, 1

+instance = comp, \SW[2]~input , SW[2]~input, ex14, 1

+instance = comp, \fin_address|Add0~9 , fin_address|Add0~9, ex14, 1

+instance = comp, \fin_address|address[2]~feeder , fin_address|address[2]~feeder, ex14, 1

+instance = comp, \fin_address|address[2] , fin_address|address[2], ex14, 1

+instance = comp, \SW[3]~input , SW[3]~input, ex14, 1

+instance = comp, \fin_address|Add0~13 , fin_address|Add0~13, ex14, 1

+instance = comp, \fin_address|address[3]~feeder , fin_address|address[3]~feeder, ex14, 1

+instance = comp, \fin_address|address[3] , fin_address|address[3], ex14, 1

+instance = comp, \SW[4]~input , SW[4]~input, ex14, 1

+instance = comp, \fin_address|Add0~17 , fin_address|Add0~17, ex14, 1

+instance = comp, \fin_address|address[4]~feeder , fin_address|address[4]~feeder, ex14, 1

+instance = comp, \fin_address|address[4] , fin_address|address[4], ex14, 1

+instance = comp, \SW[5]~input , SW[5]~input, ex14, 1

+instance = comp, \fin_address|Add0~21 , fin_address|Add0~21, ex14, 1

+instance = comp, \fin_address|address[5]~feeder , fin_address|address[5]~feeder, ex14, 1

+instance = comp, \fin_address|address[5] , fin_address|address[5], ex14, 1

+instance = comp, \SW[6]~input , SW[6]~input, ex14, 1

+instance = comp, \fin_address|Add0~25 , fin_address|Add0~25, ex14, 1

+instance = comp, \fin_address|address[6]~feeder , fin_address|address[6]~feeder, ex14, 1

+instance = comp, \fin_address|address[6] , fin_address|address[6], ex14, 1

+instance = comp, \SW[7]~input , SW[7]~input, ex14, 1

+instance = comp, \fin_address|Add0~29 , fin_address|Add0~29, ex14, 1

+instance = comp, \fin_address|address[7]~feeder , fin_address|address[7]~feeder, ex14, 1

+instance = comp, \fin_address|address[7] , fin_address|address[7], ex14, 1

+instance = comp, \SW[8]~input , SW[8]~input, ex14, 1

+instance = comp, \fin_address|Add0~33 , fin_address|Add0~33, ex14, 1

+instance = comp, \fin_address|address[8]~feeder , fin_address|address[8]~feeder, ex14, 1

+instance = comp, \fin_address|address[8] , fin_address|address[8], ex14, 1

+instance = comp, \SW[9]~input , SW[9]~input, ex14, 1

+instance = comp, \fin_address|Add0~37 , fin_address|Add0~37, ex14, 1

+instance = comp, \fin_address|address[9]~feeder , fin_address|address[9]~feeder, ex14, 1

+instance = comp, \fin_address|address[9] , fin_address|address[9], ex14, 1

+instance = comp, \rom|altsyncram_component|auto_generated|ram_block1a0 , rom|altsyncram_component|auto_generated|ram_block1a0, ex14, 1

+instance = comp, \dac|shift_reg[11]~feeder , dac|shift_reg[11]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[10]~feeder , dac|shift_reg[10]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[9]~feeder , dac|shift_reg[9]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[8]~feeder , dac|shift_reg[8]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[7]~feeder , dac|shift_reg[7]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[6]~feeder , dac|shift_reg[6]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[5]~feeder , dac|shift_reg[5]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[4]~feeder , dac|shift_reg[4]~feeder, ex14, 1

+instance = comp, \dac|shift_reg[3]~feeder , dac|shift_reg[3]~feeder, ex14, 1

+instance = comp, \dac|shift_reg~4 , dac|shift_reg~4, ex14, 1

+instance = comp, \dac|shift_reg[2] , dac|shift_reg[2], ex14, 1

+instance = comp, \dac|always5~0 , dac|always5~0, ex14, 1

+instance = comp, \dac|shift_reg[3] , dac|shift_reg[3], ex14, 1

+instance = comp, \dac|shift_reg[4] , dac|shift_reg[4], ex14, 1

+instance = comp, \dac|shift_reg[5] , dac|shift_reg[5], ex14, 1

+instance = comp, \dac|shift_reg[6] , dac|shift_reg[6], ex14, 1

+instance = comp, \dac|shift_reg[7] , dac|shift_reg[7], ex14, 1

+instance = comp, \dac|shift_reg[8] , dac|shift_reg[8], ex14, 1

+instance = comp, \dac|shift_reg[9] , dac|shift_reg[9], ex14, 1

+instance = comp, \dac|shift_reg[10] , dac|shift_reg[10], ex14, 1

+instance = comp, \dac|shift_reg[11] , dac|shift_reg[11], ex14, 1

+instance = comp, \dac|shift_reg~3 , dac|shift_reg~3, ex14, 1

+instance = comp, \dac|shift_reg[12] , dac|shift_reg[12], ex14, 1

+instance = comp, \dac|shift_reg~2 , dac|shift_reg~2, ex14, 1

+instance = comp, \dac|shift_reg[13] , dac|shift_reg[13], ex14, 1

+instance = comp, \dac|shift_reg~1 , dac|shift_reg~1, ex14, 1

+instance = comp, \dac|shift_reg[14] , dac|shift_reg[14], ex14, 1

+instance = comp, \dac|shift_reg~0 , dac|shift_reg~0, ex14, 1

+instance = comp, \dac|shift_reg[15] , dac|shift_reg[15], ex14, 1

+instance = comp, \dac|Equal2~0 , dac|Equal2~0, ex14, 1

+instance = comp, \dac|dac_sck , dac|dac_sck, ex14, 1

+instance = comp, \p|count[0]~0 , p|count[0]~0, ex14, 1

+instance = comp, \p|count[0] , p|count[0], ex14, 1

+instance = comp, \p|Add0~33 , p|Add0~33, ex14, 1

+instance = comp, \p|count[1] , p|count[1], ex14, 1

+instance = comp, \p|Add0~29 , p|Add0~29, ex14, 1

+instance = comp, \p|count[2] , p|count[2], ex14, 1

+instance = comp, \p|Add0~25 , p|Add0~25, ex14, 1

+instance = comp, \p|count[3] , p|count[3], ex14, 1

+instance = comp, \p|Add0~21 , p|Add0~21, ex14, 1

+instance = comp, \p|count[4] , p|count[4], ex14, 1

+instance = comp, \p|Add0~17 , p|Add0~17, ex14, 1

+instance = comp, \p|count[5] , p|count[5], ex14, 1

+instance = comp, \p|Add0~13 , p|Add0~13, ex14, 1

+instance = comp, \p|count[6] , p|count[6], ex14, 1

+instance = comp, \p|Add0~9 , p|Add0~9, ex14, 1

+instance = comp, \p|count[7] , p|count[7], ex14, 1

+instance = comp, \p|Add0~5 , p|Add0~5, ex14, 1

+instance = comp, \p|count[8] , p|count[8], ex14, 1

+instance = comp, \p|Add0~1 , p|Add0~1, ex14, 1

+instance = comp, \p|count[9] , p|count[9], ex14, 1

+instance = comp, \p|d[9] , p|d[9], ex14, 1

+instance = comp, \p|d[8] , p|d[8], ex14, 1

+instance = comp, \p|d[7] , p|d[7], ex14, 1

+instance = comp, \p|LessThan0~0 , p|LessThan0~0, ex14, 1

+instance = comp, \p|d[6]~feeder , p|d[6]~feeder, ex14, 1

+instance = comp, \p|d[6] , p|d[6], ex14, 1

+instance = comp, \p|d[3] , p|d[3], ex14, 1

+instance = comp, \p|d[4] , p|d[4], ex14, 1

+instance = comp, \p|d[2] , p|d[2], ex14, 1

+instance = comp, \p|d[1] , p|d[1], ex14, 1

+instance = comp, \p|d[0] , p|d[0], ex14, 1

+instance = comp, \p|count[0]~DUPLICATE , p|count[0]~DUPLICATE, ex14, 1

+instance = comp, \p|LessThan0~2 , p|LessThan0~2, ex14, 1

+instance = comp, \p|LessThan0~3 , p|LessThan0~3, ex14, 1

+instance = comp, \p|d[5] , p|d[5], ex14, 1

+instance = comp, \p|LessThan0~1 , p|LessThan0~1, ex14, 1

+instance = comp, \p|LessThan0~4 , p|LessThan0~4, ex14, 1

+instance = comp, \p|LessThan0~5 , p|LessThan0~5, ex14, 1

+instance = comp, \p|pwm_out , p|pwm_out, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][17]~5 , mult|lpm_mult_component|mult_core|romout[1][17]~5, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][17]~4 , mult|lpm_mult_component|mult_core|romout[0][17]~4, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][16]~3 , mult|lpm_mult_component|mult_core|romout[0][16]~3, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][15]~2 , mult|lpm_mult_component|mult_core|romout[0][15]~2, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[0][14]~1 , mult|lpm_mult_component|mult_core|romout[0][14]~1, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|romout[1][9]~0 , mult|lpm_mult_component|mult_core|romout[1][9]~0, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~70, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~66, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~62, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~58, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~54, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~10, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~1, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~5, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~13, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~17, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~21, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~25, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~29, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~33, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~37, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~41, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~45, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49 , mult|lpm_mult_component|mult_core|padder|adder[0]|auto_generated|op_1~49, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~1, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~5, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~9, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~13, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~17, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~21, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~25, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~29, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~33, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~37, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~41, ex14, 1

+instance = comp, \mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45 , mult|lpm_mult_component|mult_core|padder|sub_par_add|adder[0]|auto_generated|op_1~45, ex14, 1

+instance = comp, \bcd|A2|WideOr3~0 , bcd|A2|WideOr3~0, ex14, 1

+instance = comp, \bcd|A2|WideOr2~0 , bcd|A2|WideOr2~0, ex14, 1

+instance = comp, \bcd|A2|WideOr1~0 , bcd|A2|WideOr1~0, ex14, 1

+instance = comp, \bcd|A4|WideOr1~0 , bcd|A4|WideOr1~0, ex14, 1

+instance = comp, \bcd|A4|WideOr3~0 , bcd|A4|WideOr3~0, ex14, 1

+instance = comp, \bcd|A4|WideOr2~0 , bcd|A4|WideOr2~0, ex14, 1

+instance = comp, \bcd|A6|WideOr3~0 , bcd|A6|WideOr3~0, ex14, 1

+instance = comp, \bcd|A6|WideOr2~0 , bcd|A6|WideOr2~0, ex14, 1

+instance = comp, \bcd|A6|WideOr1~0 , bcd|A6|WideOr1~0, ex14, 1

+instance = comp, \bcd|A8|WideOr2~0 , bcd|A8|WideOr2~0, ex14, 1

+instance = comp, \bcd|A8|WideOr3~0 , bcd|A8|WideOr3~0, ex14, 1

+instance = comp, \bcd|A8|WideOr1~0 , bcd|A8|WideOr1~0, ex14, 1

+instance = comp, \bcd|A11|WideOr1~0 , bcd|A11|WideOr1~0, ex14, 1

+instance = comp, \bcd|A11|WideOr2~0 , bcd|A11|WideOr2~0, ex14, 1

+instance = comp, \bcd|A11|WideOr3~0 , bcd|A11|WideOr3~0, ex14, 1

+instance = comp, \bcd|A14|WideOr3~0 , bcd|A14|WideOr3~0, ex14, 1

+instance = comp, \bcd|A14|WideOr2~0 , bcd|A14|WideOr2~0, ex14, 1

+instance = comp, \bcd|A14|WideOr1~0 , bcd|A14|WideOr1~0, ex14, 1

+instance = comp, \bcd|A17|WideOr2~0 , bcd|A17|WideOr2~0, ex14, 1

+instance = comp, \bcd|A17|WideOr3~0 , bcd|A17|WideOr3~0, ex14, 1

+instance = comp, \bcd|A17|WideOr1~0 , bcd|A17|WideOr1~0, ex14, 1

+instance = comp, \bcd|A21|WideOr1~0 , bcd|A21|WideOr1~0, ex14, 1

+instance = comp, \bcd|A21|WideOr3~0 , bcd|A21|WideOr3~0, ex14, 1

+instance = comp, \bcd|A21|WideOr2~0 , bcd|A21|WideOr2~0, ex14, 1

+instance = comp, \bcd|A25|WideOr1~0 , bcd|A25|WideOr1~0, ex14, 1

+instance = comp, \bcd|A25|WideOr2~0 , bcd|A25|WideOr2~0, ex14, 1

+instance = comp, \bcd|A25|WideOr3~0 , bcd|A25|WideOr3~0, ex14, 1

+instance = comp, \bcd|A29|WideOr3~0 , bcd|A29|WideOr3~0, ex14, 1

+instance = comp, \bcd|A29|WideOr2~0 , bcd|A29|WideOr2~0, ex14, 1

+instance = comp, \bcd|A29|WideOr1~0 , bcd|A29|WideOr1~0, ex14, 1

+instance = comp, \h0|WideOr6~0 , h0|WideOr6~0, ex14, 1

+instance = comp, \h0|WideOr5~0 , h0|WideOr5~0, ex14, 1

+instance = comp, \h0|WideOr4~0 , h0|WideOr4~0, ex14, 1

+instance = comp, \h0|WideOr3~0 , h0|WideOr3~0, ex14, 1

+instance = comp, \h0|WideOr2~0 , h0|WideOr2~0, ex14, 1

+instance = comp, \h0|WideOr1~0 , h0|WideOr1~0, ex14, 1

+instance = comp, \h0|WideOr0~0 , h0|WideOr0~0, ex14, 1

+instance = comp, \bcd|A7|WideOr2~0 , bcd|A7|WideOr2~0, ex14, 1

+instance = comp, \bcd|A7|WideOr3~0 , bcd|A7|WideOr3~0, ex14, 1

+instance = comp, \bcd|A8|WideOr0~0 , bcd|A8|WideOr0~0, ex14, 1

+instance = comp, \bcd|A7|WideOr1~0 , bcd|A7|WideOr1~0, ex14, 1

+instance = comp, \bcd|A10|WideOr1~0 , bcd|A10|WideOr1~0, ex14, 1

+instance = comp, \bcd|A11|WideOr0~0 , bcd|A11|WideOr0~0, ex14, 1

+instance = comp, \bcd|A10|WideOr3~0 , bcd|A10|WideOr3~0, ex14, 1

+instance = comp, \bcd|A10|WideOr2~0 , bcd|A10|WideOr2~0, ex14, 1

+instance = comp, \bcd|A13|WideOr3~0 , bcd|A13|WideOr3~0, ex14, 1

+instance = comp, \bcd|A13|WideOr1~0 , bcd|A13|WideOr1~0, ex14, 1

+instance = comp, \bcd|A13|WideOr2~0 , bcd|A13|WideOr2~0, ex14, 1

+instance = comp, \bcd|A14|WideOr0~0 , bcd|A14|WideOr0~0, ex14, 1

+instance = comp, \bcd|A16|WideOr3~0 , bcd|A16|WideOr3~0, ex14, 1

+instance = comp, \bcd|A16|WideOr1~0 , bcd|A16|WideOr1~0, ex14, 1

+instance = comp, \bcd|A16|WideOr2~0 , bcd|A16|WideOr2~0, ex14, 1

+instance = comp, \bcd|A17|WideOr0~0 , bcd|A17|WideOr0~0, ex14, 1

+instance = comp, \bcd|A20|WideOr3~0 , bcd|A20|WideOr3~0, ex14, 1

+instance = comp, \bcd|A20|WideOr2~0 , bcd|A20|WideOr2~0, ex14, 1

+instance = comp, \bcd|A20|WideOr1~0 , bcd|A20|WideOr1~0, ex14, 1

+instance = comp, \bcd|A21|WideOr0~0 , bcd|A21|WideOr0~0, ex14, 1

+instance = comp, \bcd|A24|WideOr3~0 , bcd|A24|WideOr3~0, ex14, 1

+instance = comp, \bcd|A25|WideOr0~0 , bcd|A25|WideOr0~0, ex14, 1

+instance = comp, \bcd|A24|WideOr1~0 , bcd|A24|WideOr1~0, ex14, 1

+instance = comp, \bcd|A24|WideOr2~0 , bcd|A24|WideOr2~0, ex14, 1

+instance = comp, \bcd|A28|WideOr1~0 , bcd|A28|WideOr1~0, ex14, 1

+instance = comp, \bcd|A28|WideOr3~0 , bcd|A28|WideOr3~0, ex14, 1

+instance = comp, \bcd|A29|WideOr0~0 , bcd|A29|WideOr0~0, ex14, 1

+instance = comp, \bcd|A28|WideOr2~0 , bcd|A28|WideOr2~0, ex14, 1

+instance = comp, \h1|WideOr6~0 , h1|WideOr6~0, ex14, 1

+instance = comp, \h1|WideOr5~0 , h1|WideOr5~0, ex14, 1

+instance = comp, \h1|WideOr4~0 , h1|WideOr4~0, ex14, 1

+instance = comp, \h1|WideOr3~0 , h1|WideOr3~0, ex14, 1

+instance = comp, \h1|WideOr2~0 , h1|WideOr2~0, ex14, 1

+instance = comp, \h1|WideOr1~0 , h1|WideOr1~0, ex14, 1

+instance = comp, \h1|WideOr0~0 , h1|WideOr0~0, ex14, 1

+instance = comp, \bcd|A1|WideOr0~0 , bcd|A1|WideOr0~0, ex14, 1

+instance = comp, \bcd|A2|WideOr0~0 , bcd|A2|WideOr0~0, ex14, 1

+instance = comp, \bcd|A6|WideOr0~0 , bcd|A6|WideOr0~0, ex14, 1

+instance = comp, \bcd|A4|WideOr0~0 , bcd|A4|WideOr0~0, ex14, 1

+instance = comp, \bcd|A15|WideOr2~0 , bcd|A15|WideOr2~0, ex14, 1

+instance = comp, \bcd|A16|WideOr0~0 , bcd|A16|WideOr0~0, ex14, 1

+instance = comp, \bcd|A15|WideOr3~0 , bcd|A15|WideOr3~0, ex14, 1

+instance = comp, \bcd|A15|WideOr1~0 , bcd|A15|WideOr1~0, ex14, 1

+instance = comp, \bcd|A19|WideOr1~0 , bcd|A19|WideOr1~0, ex14, 1

+instance = comp, \bcd|A19|WideOr3~0 , bcd|A19|WideOr3~0, ex14, 1

+instance = comp, \bcd|A19|WideOr2~0 , bcd|A19|WideOr2~0, ex14, 1

+instance = comp, \bcd|A20|WideOr0~0 , bcd|A20|WideOr0~0, ex14, 1

+instance = comp, \bcd|A23|WideOr2~0 , bcd|A23|WideOr2~0, ex14, 1

+instance = comp, \bcd|A23|WideOr3~0 , bcd|A23|WideOr3~0, ex14, 1

+instance = comp, \bcd|A24|WideOr0~0 , bcd|A24|WideOr0~0, ex14, 1

+instance = comp, \bcd|A23|WideOr1~0 , bcd|A23|WideOr1~0, ex14, 1

+instance = comp, \bcd|A27|WideOr1~0 , bcd|A27|WideOr1~0, ex14, 1

+instance = comp, \bcd|A28|WideOr0~0 , bcd|A28|WideOr0~0, ex14, 1

+instance = comp, \bcd|A27|WideOr2~0 , bcd|A27|WideOr2~0, ex14, 1

+instance = comp, \bcd|A27|WideOr3~0 , bcd|A27|WideOr3~0, ex14, 1

+instance = comp, \h2|WideOr6~0 , h2|WideOr6~0, ex14, 1

+instance = comp, \h2|WideOr5~0 , h2|WideOr5~0, ex14, 1

+instance = comp, \h2|WideOr4~0 , h2|WideOr4~0, ex14, 1

+instance = comp, \h2|WideOr3~0 , h2|WideOr3~0, ex14, 1

+instance = comp, \h2|WideOr2~0 , h2|WideOr2~0, ex14, 1

+instance = comp, \h2|WideOr1~0 , h2|WideOr1~0, ex14, 1

+instance = comp, \h2|WideOr0~0 , h2|WideOr0~0, ex14, 1

+instance = comp, \bcd|A7|WideOr0~0 , bcd|A7|WideOr0~0, ex14, 1

+instance = comp, \bcd|A5|WideOr0~0 , bcd|A5|WideOr0~0, ex14, 1

+instance = comp, \bcd|A10|WideOr0~0 , bcd|A10|WideOr0~0, ex14, 1

+instance = comp, \bcd|A12|WideOr0~0 , bcd|A12|WideOr0~0, ex14, 1

+instance = comp, \bcd|A15|WideOr0~0 , bcd|A15|WideOr0~0, ex14, 1

+instance = comp, \bcd|A23|WideOr0~0 , bcd|A23|WideOr0~0, ex14, 1

+instance = comp, \bcd|A19|WideOr0~0 , bcd|A19|WideOr0~0, ex14, 1

+instance = comp, \bcd|A26|Decoder0~2 , bcd|A26|Decoder0~2, ex14, 1

+instance = comp, \bcd|A26|Decoder0~0 , bcd|A26|Decoder0~0, ex14, 1

+instance = comp, \bcd|A26|WideOr2 , bcd|A26|WideOr2, ex14, 1

+instance = comp, \bcd|A27|WideOr0~0 , bcd|A27|WideOr0~0, ex14, 1

+instance = comp, \bcd|A26|Decoder0~3 , bcd|A26|Decoder0~3, ex14, 1

+instance = comp, \bcd|A26|WideOr1 , bcd|A26|WideOr1, ex14, 1

+instance = comp, \bcd|A26|Decoder0~1 , bcd|A26|Decoder0~1, ex14, 1

+instance = comp, \bcd|A26|WideOr3~0 , bcd|A26|WideOr3~0, ex14, 1

+instance = comp, \h3|WideOr6~0 , h3|WideOr6~0, ex14, 1

+instance = comp, \h3|WideOr5~0 , h3|WideOr5~0, ex14, 1

+instance = comp, \h3|WideOr4~0 , h3|WideOr4~0, ex14, 1

+instance = comp, \h3|WideOr3~0 , h3|WideOr3~0, ex14, 1

+instance = comp, \h3|WideOr2~0 , h3|WideOr2~0, ex14, 1

+instance = comp, \h3|WideOr1~0 , h3|WideOr1~0, ex14, 1

+instance = comp, \h3|WideOr0~0 , h3|WideOr0~0, ex14, 1

+instance = comp, \bcd|A26|Decoder0~4 , bcd|A26|Decoder0~4, ex14, 1

+instance = comp, \bcd|A22|WideOr0~0 , bcd|A22|WideOr0~0, ex14, 1

+instance = comp, \h4|Decoder0~0 , h4|Decoder0~0, ex14, 1

+instance = comp, \bcd|A13|WideOr0~0 , bcd|A13|WideOr0~0, ex14, 1

+instance = comp, \h4|Decoder0~2 , h4|Decoder0~2, ex14, 1

+instance = comp, \bcd|A26|WideOr0 , bcd|A26|WideOr0, ex14, 1

+instance = comp, \h4|Decoder0~1 , h4|Decoder0~1, ex14, 1

+instance = comp, \~QUARTUS_CREATED_GND~I , ~QUARTUS_CREATED_GND~I, ex14, 1