1 files changed, 276 insertions, 0 deletions
diff --git a/part_4/ex16/db/ex16_top.hier_info b/part_4/ex16/db/ex16_top.hier_info
new file mode 100755
index 0000000..b25efc2
--- /dev/null
+++ b/part_4/ex16/db/ex16_top.hier_info
@@ -0,0 +1,276 @@
+|ex16_top
+CLOCK_50 => CLOCK_50.IN5
+SW[0] => ~NO_FANOUT~
+SW[1] => ~NO_FANOUT~
+SW[2] => ~NO_FANOUT~
+SW[3] => ~NO_FANOUT~
+SW[4] => ~NO_FANOUT~
+SW[5] => ~NO_FANOUT~
+SW[6] => ~NO_FANOUT~
+SW[7] => ~NO_FANOUT~
+SW[8] => ~NO_FANOUT~
+SW[9] => ~NO_FANOUT~
+HEX0[0] << hex_to_7seg:SEG0.port0
+HEX0[1] << hex_to_7seg:SEG0.port0
+HEX0[2] << hex_to_7seg:SEG0.port0
+HEX0[3] << hex_to_7seg:SEG0.port0
+HEX0[4] << hex_to_7seg:SEG0.port0
+HEX0[5] << hex_to_7seg:SEG0.port0
+HEX0[6] << hex_to_7seg:SEG0.port0
+HEX1[0] << hex_to_7seg:SEG1.port0
+HEX1[1] << hex_to_7seg:SEG1.port0
+HEX1[2] << hex_to_7seg:SEG1.port0
+HEX1[3] << hex_to_7seg:SEG1.port0
+HEX1[4] << hex_to_7seg:SEG1.port0
+HEX1[5] << hex_to_7seg:SEG1.port0
+HEX1[6] << hex_to_7seg:SEG1.port0
+HEX2[0] << hex_to_7seg:SEG2.port0
+HEX2[1] << hex_to_7seg:SEG2.port0
+HEX2[2] << hex_to_7seg:SEG2.port0
+HEX2[3] << hex_to_7seg:SEG2.port0
+HEX2[4] << hex_to_7seg:SEG2.port0
+HEX2[5] << hex_to_7seg:SEG2.port0
+HEX2[6] << hex_to_7seg:SEG2.port0
+DAC_SDI << spi2dac:SPI_DAC.port3
+DAC_SCK << spi2dac:SPI_DAC.port5
+DAC_CS << spi2dac:SPI_DAC.port4
+DAC_LD << spi2dac:SPI_DAC.port6
+ADC_SDI << spi2adc:SPI_ADC.sdata_to_adc
+ADC_SCK << spi2adc:SPI_ADC.adc_sck
+ADC_CS << spi2adc:SPI_ADC.adc_cs
+ADC_SDO => ADC_SDO.IN1
+PWM_OUT << pwm:PWM_DC.port3
+
+
+|ex16_top|clktick_16:GEN_10K
+clkin => count[0].CLK
+clkin => count[1].CLK
+clkin => count[2].CLK
+clkin => count[3].CLK
+clkin => count[4].CLK
+clkin => count[5].CLK
+clkin => count[6].CLK
+clkin => count[7].CLK
+clkin => count[8].CLK
+clkin => count[9].CLK
+clkin => count[10].CLK
+clkin => count[11].CLK
+clkin => count[12].CLK
+clkin => count[13].CLK
+clkin => count[14].CLK
+clkin => count[15].CLK
+clkin => tick~reg0.CLK
+enable => count[0].ENA
+enable => count[1].ENA
+enable => count[2].ENA
+enable => count[3].ENA
+enable => count[4].ENA
+enable => count[5].ENA
+enable => count[6].ENA
+enable => count[7].ENA
+enable => count[8].ENA
+enable => count[9].ENA
+enable => count[10].ENA
+enable => count[11].ENA
+enable => count[12].ENA
+enable => count[13].ENA
+enable => count[14].ENA
+enable => count[15].ENA
+enable => tick~reg0.ENA
+N[0] => count.DATAB
+N[1] => count.DATAB
+N[2] => count.DATAB
+N[3] => count.DATAB
+N[4] => count.DATAB
+N[5] => count.DATAB
+N[6] => count.DATAB
+N[7] => count.DATAB
+N[8] => count.DATAB
+N[9] => count.DATAB
+N[10] => count.DATAB
+N[11] => count.DATAB
+N[12] => count.DATAB
+N[13] => count.DATAB
+N[14] => count.DATAB
+N[15] => count.DATAB
+tick <= tick~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|spi2dac:SPI_DAC
+clk => dac_start.CLK
+clk => clk_1MHz.CLK
+clk => ctr[0].CLK
+clk => ctr[1].CLK
+clk => ctr[2].CLK
+clk => ctr[3].CLK
+clk => ctr[4].CLK
+clk => sr_state~1.DATAIN
+data_in[0] => shift_reg.DATAB
+data_in[1] => shift_reg.DATAB
+data_in[2] => shift_reg.DATAB
+data_in[3] => shift_reg.DATAB
+data_in[4] => shift_reg.DATAB
+data_in[5] => shift_reg.DATAB
+data_in[6] => shift_reg.DATAB
+data_in[7] => shift_reg.DATAB
+data_in[8] => shift_reg.DATAB
+data_in[9] => shift_reg.DATAB
+load => Selector1.IN1
+load => dac_start.OUTPUTSELECT
+load => Selector0.IN1
+dac_sdi <= shift_reg[15].DB_MAX_OUTPUT_PORT_TYPE
+dac_cs <= dac_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dac_sck <= dac_sck.DB_MAX_OUTPUT_PORT_TYPE
+dac_ld <= dac_ld~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|pwm:PWM_DC
+clk => pwm_out~reg0.CLK
+clk => count[0].CLK
+clk => count[1].CLK
+clk => count[2].CLK
+clk => count[3].CLK
+clk => count[4].CLK
+clk => count[5].CLK
+clk => count[6].CLK
+clk => count[7].CLK
+clk => count[8].CLK
+clk => count[9].CLK
+clk => d[0].CLK
+clk => d[1].CLK
+clk => d[2].CLK
+clk => d[3].CLK
+clk => d[4].CLK
+clk => d[5].CLK
+clk => d[6].CLK
+clk => d[7].CLK
+clk => d[8].CLK
+clk => d[9].CLK
+data_in[0] => d[0].DATAIN
+data_in[1] => d[1].DATAIN
+data_in[2] => d[2].DATAIN
+data_in[3] => d[3].DATAIN
+data_in[4] => d[4].DATAIN
+data_in[5] => d[5].DATAIN
+data_in[6] => d[6].DATAIN
+data_in[7] => d[7].DATAIN
+data_in[8] => d[8].DATAIN
+data_in[9] => d[9].DATAIN
+load => d[0].ENA
+load => d[1].ENA
+load => d[2].ENA
+load => d[3].ENA
+load => d[4].ENA
+load => d[5].ENA
+load => d[6].ENA
+load => d[7].ENA
+load => d[8].ENA
+load => d[9].ENA
+pwm_out <= pwm_out~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|spi2adc:SPI_ADC
+sysclk => adc_start.CLK
+sysclk => clk_1MHz.CLK
+sysclk => ctr[0].CLK
+sysclk => ctr[1].CLK
+sysclk => ctr[2].CLK
+sysclk => ctr[3].CLK
+sysclk => ctr[4].CLK
+sysclk => sr_state~1.DATAIN
+start => Selector1.IN1
+start => adc_start.OUTPUTSELECT
+start => Selector0.IN1
+channel => Selector6.IN6
+data_from_adc[0] <= data_from_adc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[1] <= data_from_adc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[2] <= data_from_adc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[3] <= data_from_adc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[4] <= data_from_adc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[5] <= data_from_adc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[6] <= data_from_adc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[7] <= data_from_adc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[8] <= data_from_adc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_from_adc[9] <= data_from_adc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_valid <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+sdata_to_adc <= adc_din.DB_MAX_OUTPUT_PORT_TYPE
+adc_cs <= adc_cs~reg0.DB_MAX_OUTPUT_PORT_TYPE
+adc_sck <= adc_sck.DB_MAX_OUTPUT_PORT_TYPE
+sdata_from_adc => shift_reg[0].DATAIN
+
+
+|ex16_top|processor:ALLPASS
+sysclk => data_out[0]~reg0.CLK
+sysclk => data_out[1]~reg0.CLK
+sysclk => data_out[2]~reg0.CLK
+sysclk => data_out[3]~reg0.CLK
+sysclk => data_out[4]~reg0.CLK
+sysclk => data_out[5]~reg0.CLK
+sysclk => data_out[6]~reg0.CLK
+sysclk => data_out[7]~reg0.CLK
+sysclk => data_out[8]~reg0.CLK
+sysclk => data_out[9]~reg0.CLK
+data_in[0] => Add0.IN20
+data_in[1] => Add0.IN19
+data_in[2] => Add0.IN18
+data_in[3] => Add0.IN17
+data_in[4] => Add0.IN16
+data_in[5] => Add0.IN15
+data_in[6] => Add0.IN14
+data_in[7] => Add0.IN13
+data_in[8] => Add0.IN12
+data_in[9] => Add0.IN11
+data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_out[9] <= data_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|ex16_top|hex_to_7seg:SEG0
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex16_top|hex_to_7seg:SEG1
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+
+|ex16_top|hex_to_7seg:SEG2
+out[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
+out[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
+out[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
+out[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
+out[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
+out[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
+out[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
+in[0] => Decoder0.IN3
+in[1] => Decoder0.IN2
+in[2] => Decoder0.IN1
+in[3] => Decoder0.IN0
+
+