diff options
Diffstat (limited to 'part_4/ex18/verilog_files/echo_synth.v.bak')
| -rwxr-xr-x | part_4/ex18/verilog_files/echo_synth.v.bak | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/part_4/ex18/verilog_files/echo_synth.v.bak b/part_4/ex18/verilog_files/echo_synth.v.bak new file mode 100755 index 0000000..91d95dc --- /dev/null +++ b/part_4/ex18/verilog_files/echo_synth.v.bak @@ -0,0 +1,27 @@ +module processor (sysclk, data_in, data_out);
+
+ input sysclk; // system clock
+ input [9:0] data_in; // 10-bit input data
+ output [9:0] data_out; // 10-bit output data
+
+ wire sysclk;
+ wire [9:0] data_in;
+ reg [9:0] data_out;
+ wire [9:0] x,y;
+
+ parameter ADC_OFFSET = 10'h181;
+ parameter DAC_OFFSET = 10'h200;
+
+ assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement
+
+ // This part should include your own processing hardware
+ // ... that takes x to produce y
+ // ... In this case, it is ALL PASS.
+ assign y = x;
+
+ // Now clock y output with system clock
+ always @(posedge sysclk)
+ data_out <= y + DAC_OFFSET;
+
+endmodule
+
\ No newline at end of file |