diff options
Diffstat (limited to 'part_4/ex19/db/ex19.map.qmsg')
| -rwxr-xr-x | part_4/ex19/db/ex19.map.qmsg | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/part_4/ex19/db/ex19.map.qmsg b/part_4/ex19/db/ex19.map.qmsg new file mode 100755 index 0000000..52a9905 --- /dev/null +++ b/part_4/ex19/db/ex19.map.qmsg @@ -0,0 +1,110 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1481017578667 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1481017578668 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 06 09:46:18 2016 " "Processing started: Tue Dec 06 09:46:18 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1481017578668 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017578668 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19 " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex19 -c ex19" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017578669 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1481017579170 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1481017579171 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/variable_echo.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/variable_echo.v" { { "Info" "ISGN_ENTITY_NAME" "1 processor " "Found entity 1: processor" { } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587579 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2dac.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2dac.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2dac " "Found entity 1: spi2dac" { } { { "verilog_files/spi2dac.v" "" { Text "C:/New folder/ex19/verilog_files/spi2dac.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587581 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/spi2adc.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/spi2adc.v" { { "Info" "ISGN_ENTITY_NAME" "1 spi2adc " "Found entity 1: spi2adc" { } { { "verilog_files/spi2adc.v" "" { Text "C:/New folder/ex19/verilog_files/spi2adc.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587583 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587583 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pwm.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pwm.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Found entity 1: pwm" { } { { "verilog_files/pwm.v" "" { Text "C:/New folder/ex19/verilog_files/pwm.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587585 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587585 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/pulse_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/pulse_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_gen " "Found entity 1: pulse_gen" { } { { "verilog_files/pulse_gen.v" "" { Text "C:/New folder/ex19/verilog_files/pulse_gen.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587586 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587586 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/multiply_k.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/multiply_k.v" { { "Info" "ISGN_ENTITY_NAME" "1 multiply_k " "Found entity 1: multiply_k" { } { { "verilog_files/multiply_k.v" "" { Text "C:/New folder/ex19/verilog_files/multiply_k.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587588 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587588 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/hex_to_7seg.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/hex_to_7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 hex_to_7seg " "Found entity 1: hex_to_7seg" { } { { "verilog_files/hex_to_7seg.v" "" { Text "C:/New folder/ex19/verilog_files/hex_to_7seg.v" 10 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587590 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587590 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/div_by_2.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/div_by_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 div_by_2 " "Found entity 1: div_by_2" { } { { "verilog_files/div_by_2.v" "" { Text "C:/New folder/ex19/verilog_files/div_by_2.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587591 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587591 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_ram " "Found entity 1: delay_ram" { } { { "verilog_files/delay_ram.v" "" { Text "C:/New folder/ex19/verilog_files/delay_ram.v" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587593 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587593 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/d_ff.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/d_ff.v" { { "Info" "ISGN_ENTITY_NAME" "1 d_ff " "Found entity 1: d_ff" { } { { "verilog_files/d_ff.v" "" { Text "C:/New folder/ex19/verilog_files/d_ff.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587595 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587595 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/clktick_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/clktick_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 clktick_16 " "Found entity 1: clktick_16" { } { { "verilog_files/clktick_16.v" "" { Text "C:/New folder/ex19/verilog_files/clktick_16.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587596 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a1 A1 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a1\" differs only in case from object \"A1\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a2 A2 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a2\" differs only in case from object \"A2\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a3 A3 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a3\" differs only in case from object \"A3\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a4 A4 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a4\" differs only in case from object \"A4\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a5 A5 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a5\" differs only in case from object \"A5\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a6 A6 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a6\" differs only in case from object \"A6\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a7 A7 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a7\" differs only in case from object \"A7\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a8 A8 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a8\" differs only in case from object \"A8\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a9 A9 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a9\" differs only in case from object \"A9\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587598 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a10 A10 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a10\" differs only in case from object \"A10\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a11 A11 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a11\" differs only in case from object \"A11\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a12 A12 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a12\" differs only in case from object \"A12\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a13 A13 bin2bcd_16.v(20) " "Verilog HDL Declaration information at bin2bcd_16.v(20): object \"a13\" differs only in case from object \"A13\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 20 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a14 A14 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a14\" differs only in case from object \"A14\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a15 A15 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a15\" differs only in case from object \"A15\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a16 A16 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a16\" differs only in case from object \"A16\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a17 A17 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a17\" differs only in case from object \"A17\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a18 A18 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a18\" differs only in case from object \"A18\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a19 A19 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a19\" differs only in case from object \"A19\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a20 A20 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a20\" differs only in case from object \"A20\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a21 A21 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a21\" differs only in case from object \"A21\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a22 A22 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a22\" differs only in case from object \"A22\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a23 A23 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a23\" differs only in case from object \"A23\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a24 A24 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a24\" differs only in case from object \"A24\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a25 A25 bin2bcd_16.v(21) " "Verilog HDL Declaration information at bin2bcd_16.v(21): object \"a25\" differs only in case from object \"A25\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 21 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a26 A26 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a26\" differs only in case from object \"A26\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a27 A27 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a27\" differs only in case from object \"A27\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a28 A28 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a28\" differs only in case from object \"A28\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a29 A29 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a29\" differs only in case from object \"A29\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a30 A30 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a30\" differs only in case from object \"A30\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a31 A31 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a31\" differs only in case from object \"A31\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a32 A32 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a32\" differs only in case from object \"A32\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a33 A33 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a33\" differs only in case from object \"A33\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a34 A34 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a34\" differs only in case from object \"A34\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "a35 A35 bin2bcd_16.v(22) " "Verilog HDL Declaration information at bin2bcd_16.v(22): object \"a35\" differs only in case from object \"A35\" in the same scope" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 22 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1481017587599 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/bin2bcd_16.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/bin2bcd_16.v" { { "Info" "ISGN_ENTITY_NAME" "1 bin2bcd_16 " "Found entity 1: bin2bcd_16" { } { { "verilog_files/bin2bcd_16.v" "" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 12 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587600 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587600 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/add3_ge5.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/add3_ge5.v" { { "Info" "ISGN_ENTITY_NAME" "1 add3_ge5 " "Found entity 1: add3_ge5" { } { { "verilog_files/add3_ge5.v" "" { Text "C:/New folder/ex19/verilog_files/add3_ge5.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587601 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587601 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ex19.v 1 1 " "Found 1 design units, including 1 entities, in source file ex19.v" { { "Info" "ISGN_ENTITY_NAME" "1 ex19 " "Found entity 1: ex19" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587603 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587603 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/delay_block.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/delay_block.v" { { "Info" "ISGN_ENTITY_NAME" "1 delay_block " "Found entity 1: delay_block" { } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587604 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587604 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "verilog_files/ctr_13_bit.v 1 1 " "Found 1 design units, including 1 entities, in source file verilog_files/ctr_13_bit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ctr_13_bit " "Found entity 1: ctr_13_bit" { } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587606 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587606 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "mult_by_h666.v 1 1 " "Found 1 design units, including 1 entities, in source file mult_by_h666.v" { { "Info" "ISGN_ENTITY_NAME" "1 mult_by_h666 " "Found entity 1: mult_by_h666" { } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587608 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587608 ""}
+{ "Critical Warning" "WVRFX_VERI_INSTANCE_NEEDS_NAME" "variable_echo.v(32) " "Verilog HDL Instantiation warning at variable_echo.v(32): instance has no name" { } { { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } } } 1 10846 "Verilog HDL Instantiation warning at %1!s!: instance has no name" 0 0 "Analysis & Synthesis" 0 -1 1481017587608 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "ex19 " "Elaborating entity \"ex19\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1481017587729 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clktick_16 clktick_16:GEN_10K " "Elaborating entity \"clktick_16\" for hierarchy \"clktick_16:GEN_10K\"" { } { { "ex19.v" "GEN_10K" { Text "C:/New folder/ex19/ex19.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587731 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2dac spi2dac:SPI_DAC " "Elaborating entity \"spi2dac\" for hierarchy \"spi2dac:SPI_DAC\"" { } { { "ex19.v" "SPI_DAC" { Text "C:/New folder/ex19/ex19.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587732 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm pwm:PWM_DC " "Elaborating entity \"pwm\" for hierarchy \"pwm:PWM_DC\"" { } { { "ex19.v" "PWM_DC" { Text "C:/New folder/ex19/ex19.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spi2adc spi2adc:SPI_ADC " "Elaborating entity \"spi2adc\" for hierarchy \"spi2adc:SPI_ADC\"" { } { { "ex19.v" "SPI_ADC" { Text "C:/New folder/ex19/ex19.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "processor processor:echo_var_delay " "Elaborating entity \"processor\" for hierarchy \"processor:echo_var_delay\"" { } { { "ex19.v" "echo_var_delay" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587735 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ctr_13_bit processor:echo_var_delay\|ctr_13_bit:ctr " "Elaborating entity \"ctr_13_bit\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\"" { } { { "verilog_files/variable_echo.v" "ctr" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 28 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587749 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborating entity \"lpm_counter\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" { } { { "verilog_files/ctr_13_bit.v" "LPM_COUNTER_component" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587786 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\"" { } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587787 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component " "Instantiated megafunction \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction UP " "Parameter \"lpm_direction\" = \"UP\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_port_updown PORT_UNUSED " "Parameter \"lpm_port_updown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_COUNTER " "Parameter \"lpm_type\" = \"LPM_COUNTER\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 13 " "Parameter \"lpm_width\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587787 ""} } { { "verilog_files/ctr_13_bit.v" "" { Text "C:/New folder/ex19/verilog_files/ctr_13_bit.v" 65 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587787 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cjh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_cjh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cjh " "Found entity 1: cntr_cjh" { } { { "db/cntr_cjh.tdf" "" { Text "C:/New folder/ex19/db/cntr_cjh.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587829 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587829 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_cjh processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated " "Elaborating entity \"cntr_cjh\" for hierarchy \"processor:echo_var_delay\|ctr_13_bit:ctr\|lpm_counter:LPM_COUNTER_component\|cntr_cjh:auto_generated\"" { } { { "lpm_counter.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_counter.tdf" 259 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587829 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_block processor:echo_var_delay\|delay_block:del " "Elaborating entity \"delay_block\" for hierarchy \"processor:echo_var_delay\|delay_block:del\"" { } { { "verilog_files/variable_echo.v" "del" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587837 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" { } { { "verilog_files/delay_block.v" "altsyncram_component" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587877 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\"" { } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587880 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component " "Instantiated megafunction \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8192 " "Parameter \"numwords_b\" = \"8192\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b CLOCK0 " "Parameter \"outdata_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M10K " "Parameter \"ram_block_type\" = \"M10K\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 13 " "Parameter \"widthad_b\" = \"13\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587880 ""} } { { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587880 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nm22.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nm22.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nm22 " "Found entity 1: altsyncram_nm22" { } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017587924 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017587924 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_nm22 processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated " "Elaborating entity \"altsyncram_nm22\" for hierarchy \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587924 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div_by_2 processor:echo_var_delay\|div_by_2:comb_6 " "Elaborating entity \"div_by_2\" for hierarchy \"processor:echo_var_delay\|div_by_2:comb_6\"" { } { { "verilog_files/variable_echo.v" "comb_6" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587929 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_by_h666 processor:echo_var_delay\|mult_by_h666:mul_by_h666 " "Elaborating entity \"mult_by_h666\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\"" { } { { "verilog_files/variable_echo.v" "mul_by_h666" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587935 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mult processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborating entity \"lpm_mult\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "mult_by_h666.v" "lpm_mult_component" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587963 ""}
+{ "Info" "ISGN_ELABORATION_HEADER" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587964 ""}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Instantiated megafunction \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5 " "Parameter \"lpm_hint\" = \"INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Parameter \"lpm_representation\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_MULT " "Parameter \"lpm_type\" = \"LPM_MULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widtha 9 " "Parameter \"lpm_widtha\" = \"9\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthb 11 " "Parameter \"lpm_widthb\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthp 20 " "Parameter \"lpm_widthp\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1481017587964 ""} } { { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1481017587964 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multcore processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core " "Elaborating entity \"multcore\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\"" { } { { "lpm_mult.tdf" "mult_core" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587995 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 309 5 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017587998 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\"" { } { { "multcore.tdf" "padder" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588017 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "multcore.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/multcore.tdf" 229 7 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588019 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\"" { } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588046 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588047 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_a9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_a9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_a9h " "Found entity 1: add_sub_a9h" { } { { "db/add_sub_a9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_a9h.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017588088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017588088 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_a9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated " "Elaborating entity \"add_sub_a9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[0\]\|add_sub_a9h:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588088 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mpar_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add " "Elaborating entity \"mpar_add\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\"" { } { { "mpar_add.tdf" "sub_par_add" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588092 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588092 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] " "Elaborating entity \"lpm_add_sub\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\"" { } { { "mpar_add.tdf" "adder\[0\]" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588096 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588097 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_e9h.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_e9h.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_e9h " "Found entity 1: add_sub_e9h" { } { { "db/add_sub_e9h.tdf" "" { Text "C:/New folder/ex19/db/add_sub_e9h.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1481017588138 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017588138 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_e9h processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated " "Elaborating entity \"add_sub_e9h\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\|add_sub_e9h:auto_generated\"" { } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588138 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs " "Elaborating entity \"altshift\" for hierarchy \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\"" { } { { "lpm_mult.tdf" "external_latency_ffs" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588157 ""}
+{ "Info" "ISGN_MEGAFN_DESCENDANT" "processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component " "Elaborated megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"processor:echo_var_delay\|mult_by_h666:mul_by_h666\|lpm_mult:lpm_mult_component\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/lpm_mult.tdf" 352 4 0 } } { "mult_by_h666.v" "" { Text "C:/New folder/ex19/mult_by_h666.v" 59 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588157 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2bcd_16 processor:echo_var_delay\|bin2bcd_16:bcd " "Elaborating entity \"bin2bcd_16\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\"" { } { { "verilog_files/variable_echo.v" "bcd" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 36 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588158 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add3_ge5 processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1 " "Elaborating entity \"add3_ge5\" for hierarchy \"processor:echo_var_delay\|bin2bcd_16:bcd\|add3_ge5:A1\"" { } { { "verilog_files/bin2bcd_16.v" "A1" { Text "C:/New folder/ex19/verilog_files/bin2bcd_16.v" 26 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588160 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex_to_7seg processor:echo_var_delay\|hex_to_7seg:h0 " "Elaborating entity \"hex_to_7seg\" for hierarchy \"processor:echo_var_delay\|hex_to_7seg:h0\"" { } { { "verilog_files/variable_echo.v" "h0" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 38 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017588167 ""}
+{ "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_TOP" "" "Net is missing source, defaulting to GND" { { "Warning" "WSGN_TRI_BUS_MISSING_SOURCE_SUB" "processor:echo_var_delay\|tmp_data\[9\] " "Net \"processor:echo_var_delay\|tmp_data\[9\]\" is missing source, defaulting to GND" { } { { "verilog_files/variable_echo.v" "tmp_data\[9\]" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 15 -1 0 } } } 0 12110 "Net \"%1!s!\" is missing source, defaulting to GND" 0 0 "Design Software" 0 -1 1481017588209 ""} } { } 0 12011 "Net is missing source, defaulting to GND" 0 0 "Analysis & Synthesis" 0 -1 1481017588209 ""}
+{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\] " "Synthesized away node \"processor:echo_var_delay\|delay_block:del\|altsyncram:altsyncram_component\|altsyncram_nm22:auto_generated\|q_b\[0\]\"" { } { { "db/altsyncram_nm22.tdf" "" { Text "C:/New folder/ex19/db/altsyncram_nm22.tdf" 39 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } { "verilog_files/delay_block.v" "" { Text "C:/New folder/ex19/verilog_files/delay_block.v" 92 0 0 } } { "verilog_files/variable_echo.v" "" { Text "C:/New folder/ex19/verilog_files/variable_echo.v" 30 0 0 } } { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 40 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017588289 "|ex19|processor:echo_var_delay|delay_block:del|altsyncram:altsyncram_component|altsyncram_nm22:auto_generated|ram_block1a0"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1481017588289 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1481017588289 ""}
+{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "4 " "4 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1481017588762 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] GND " "Pin \"HEX3\[1\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] GND " "Pin \"HEX3\[2\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[0\] GND " "Pin \"HEX4\[0\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[1\] GND " "Pin \"HEX4\[1\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[2\] GND " "Pin \"HEX4\[2\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[3\] GND " "Pin \"HEX4\[3\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[4\] GND " "Pin \"HEX4\[4\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[5\] GND " "Pin \"HEX4\[5\]\" is stuck at GND" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX4\[6\] VCC " "Pin \"HEX4\[6\]\" is stuck at VCC" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1481017588860 "|ex19|HEX4[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1481017588860 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1481017588940 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/New folder/ex19/output_files/ex19.map.smsg " "Generated suppressed messages file C:/New folder/ex19/output_files/ex19.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017589229 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1481017589331 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1481017589331 ""}
+{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "SW\[9\] " "No output dependent on input pin \"SW\[9\]\"" { } { { "ex19.v" "" { Text "C:/New folder/ex19/ex19.v" 6 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1481017589402 "|ex19|SW[9]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1481017589402 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "312 " "Implemented 312 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Implemented 12 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_OPINS" "43 " "Implemented 43 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_LCELLS" "249 " "Implemented 249 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1481017589404 ""} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Implemented 8 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1481017589404 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1481017589404 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "916 " "Peak virtual memory: 916 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 06 09:46:29 2016 " "Processing ended: Tue Dec 06 09:46:29 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1481017589423 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1481017589423 ""}
|