1 files changed, 81 insertions, 0 deletions
diff --git a/part_4/ex19/verilog_files/ctr_13_bit_bb.v b/part_4/ex19/verilog_files/ctr_13_bit_bb.v
new file mode 100755
index 0000000..908f22d
--- /dev/null
+++ b/part_4/ex19/verilog_files/ctr_13_bit_bb.v
@@ -0,0 +1,81 @@
+// megafunction wizard: %LPM_COUNTER%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: LPM_COUNTER 
+
+// ============================================================
+// File Name: ctr_13_bit.v
+// Megafunction Name(s):
+// 			LPM_COUNTER
+//
+// Simulation Library Files(s):
+// 			lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
+// ************************************************************
+
+//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, the Altera Quartus Prime License Agreement,
+//the Altera MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Altera and sold by Altera or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+module ctr_13_bit (
+	clock,
+	q);
+
+	input	  clock;
+	output	[12:0]  q;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACLR NUMERIC "0"
+// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+// Retrieval info: PRIVATE: ASET NUMERIC "0"
+// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+// Retrieval info: PRIVATE: Direction NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+// Retrieval info: PRIVATE: SCLR NUMERIC "0"
+// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+// Retrieval info: PRIVATE: SSET NUMERIC "0"
+// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: nBit NUMERIC "13"
+// Retrieval info: PRIVATE: new_diagram STRING "1"
+// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "13"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: q 0 0 13 0 OUTPUT NODEFVAL "q[12..0]"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 13 0 @q 0 0 13 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL ctr_13_bit_bb.v TRUE
+// Retrieval info: LIB_FILE: lpm