diff options
Diffstat (limited to 'part_4/ex19/verilog_files/mult_echo_synth.v.bak')
| -rwxr-xr-x | part_4/ex19/verilog_files/mult_echo_synth.v.bak | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/part_4/ex19/verilog_files/mult_echo_synth.v.bak b/part_4/ex19/verilog_files/mult_echo_synth.v.bak new file mode 100755 index 0000000..d5507b5 --- /dev/null +++ b/part_4/ex19/verilog_files/mult_echo_synth.v.bak @@ -0,0 +1,34 @@ +module processor (sysclk, tick, data_in, data_out);
+
+ input sysclk, tick; // system clock
+ input [9:0] data_in; // 10-bit input data
+ output [9:0] data_out; // 10-bit output data
+
+ wire sysclk;
+ wire [9:0] data_in;
+ reg [9:0] data_out;
+ wire [9:0] x,y;
+ wire [9:0] tmp_data, echoed_data;
+ wire is_full, and_if, from_dff;
+
+ parameter ADC_OFFSET = 10'h181;
+ parameter DAC_OFFSET = 10'h200;
+
+ assign x = data_in[9:0] - ADC_OFFSET; // x is input in 2's complement
+
+ FIFO fifo(sysclk, x, and_if, tick, is_full, tmp_data);
+
+ d_ff d(tick, is_full, from_dff);
+
+ assign and_if = tick & from_dff;
+
+ div_by_2(tmp_data, echoed_data);
+
+ assign y = x + echoed_data;
+
+ // Now clock y output with system clock
+ always @(posedge sysclk)
+ data_out <= y + DAC_OFFSET;
+
+endmodule
+
\ No newline at end of file |