summaryrefslogtreecommitdiffstats
path: root/part_1/README.md
blob: c575738d65235997fba6284eca085e3aabe69a5b (plain)
1
2
# Experiment VERI: FPGA Design with Verilog (Part 1)
In this experiment we will be programming a Cyclone V FPGA from Altera on a DE1-SoC Board that was made by Terasicas. We will mainy be