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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 232 112)
(text "My7seg" (rect 5 0 61 16)(font "Arial" (font_size 8)))
(text "inst" (rect 8 78 41 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "in[3..0]" (rect 0 0 75 16)(font "Arial" (font_size 8)))
(text "in[3..0]" (rect 21 27 96 43)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 216 32)
(output)
(text "out[6..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
(text "out[6..0]" (rect 111 27 195 43)(font "Arial" (font_size 8)))
(line (pt 216 32)(pt 200 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 200 80))
)
)
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