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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1479209419389 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analyze Current File Quartus Prime " "Running Quartus Prime Analyze Current File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 15 11:30:19 2016 " "Processing started: Tue Nov 15 11:30:19 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 --analyze_file=H:/VERI/part_1/ex4/verilog_files/add3_ge5.v " "Command: quartus_map --read_settings_files=on --write_settings_files=off ex4 -c ex4 --analyze_file=H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1479209419391 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Design Software" 0 -1 1479209419876 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Design Software" 0 -1 1479209419876 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"input\"; expecting \";\" add3_ge5.v(3) " "Verilog HDL syntax error at add3_ge5.v(3) near text: \"input\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 3 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Design Software" 0 -1 1479209428595 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"always\"; expecting \";\" add3_ge5.v(5) " "Verilog HDL syntax error at add3_ge5.v(5) near text: \"always\"; expecting \";\". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 5 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Design Software" 0 -1 1479209428595 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "add3_ge5 add3_ge5.v(1) " "Ignored design unit \"add3_ge5\" at add3_ge5.v(1) due to previous errors" { } { { "verilog_files/add3_ge5.v" "" { Text "H:/VERI/part_1/ex4/verilog_files/add3_ge5.v" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Design Software" 0 -1 1479209428601 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analyze Current File 3 s 1 Quartus Prime " "Quartus Prime Analyze Current File was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "831 " "Peak virtual memory: 831 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Nov 15 11:30:28 2016 " "Processing ended: Tue Nov 15 11:30:28 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1479209428607 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1479209428607 ""}
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