tb_counter « modelsim « simulation « ex5 « part_2 - VerilogCoursework - Unnamed repository; edit this file 'description' to name the repository.

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blob: 4544d6aec9af16d851b5b643c2a15e462f0c6bf6 (plain)

add wave clock enable
add wave -hexadecimal count
force clock 0 0, 1 10ns -repeat 20ns
force enable 1
run 100ns
force enable 0
run 100ns
force enable 1
run 1000