part_2/ex5/verilog files/ex5.v.bak


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`timescale 1ns / 100ps

module counter_8(
	clock,
	enable,
	count
	);

	parameter BIT_SZ = 8;
	input clock;
	input enable;
	output [BIT_SZ-1:0] count;
	
	reg [BIT_SZ-1:0] count;
	
	initial count = 0;
	
	always @ (posedge clock)
		if(enable == 1'b1)
			count <= count + 1'b1;
			
endmodule