blob: ae430a88760dd12fd4d590a7680f8397f506f746 (
plain)
1
2
3
4
5
6
7
8
9
10
11
|
module LFSR(CLK, COUNT);
input CLK;
output[7:0] COUNT;
reg[7:0] COUNT;
initial COUNT = 7'b1;
always @ (posedge CLK)
COUNT <= {COUNT[6:0], COUNT[7] ^ COUNT[1]};
endmodule
|