part_2/ex9_final/verilog_files/LFSR.v.bak


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module LFSR(CLK, COUNT);
	input CLK;
	output[7:1] COUNT;
	reg[7:1] COUNT;
	initial COUNT = 7'd1;
		
	always @ (posedge CLK)
		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
		
endmodule