blob: 79c144cf4699ef809f8bc6e7a69d7b28e1ef5eb8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
module counter_16(clock, start, stop, count);
parameter BIT_SZ = 16;
input clock, start, stop;
output [BIT_SZ-1:0] count;
reg [BIT_SZ-1:0] count;
reg state;
parameter COUNTING = 1'b1, IDLE = 1'b0;
initial count = 0;
initial state = IDLE;
always @ (posedge clock)
case(state)
IDLE:
if(start == 1'b1)
begin
count = 0;
state = COUNTING;
end
COUNTING:
if(stop == 1'b1)
state <= IDLE;
else
count <= count + 1'b1;
endcase
endmodule
|
