part_2/ex9_final/verilog_files/tick_50000.v.bak


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module tick_50000(CLOCK_IN, CLK_OUT);

	parameter NBIT = 16;
	
	input CLOCK_IN;
	output CLK_OUT;
	
	reg [NBIT-1:0] count;
	
	reg CLK_OUT;
	
	initial 
		begin
			count = 16'd24999;
			CLK_OUT = 1'b0;
		end
	
	always @ (posedge CLOCK_IN)
		begin
			if(count == 16'b0)
				begin
					CLK_OUT <= ~CLK_OUT;
					count <= 16'd24999;
				end
			else
				begin
					count <= count - 1'b1;
				end
		end

endmodule