ex10.smp_dump.txt « db « ex10 « part_3 - VerilogCoursework - Unnamed repository; edit this file 'description' to name the repository.

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State Machine - |ex10|spi2dac:s|sr_state
Name sr_state.IDLE sr_state.WAIT_CSB_HIGH sr_state.WAIT_CSB_FALL 
sr_state.IDLE 0 0 0 
sr_state.WAIT_CSB_FALL 1 0 1 
sr_state.WAIT_CSB_HIGH 1 1 0