index
:
VerilogCoursework
master
Unnamed repository; edit this file 'description' to name the repository.
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
part_4
/
ex16
Mode
Name
Size
-rwxr-xr-x
add3_ge5.v
780
log
stats
plain
-rwxr-xr-x
allpass.v
909
log
stats
plain
-rwxr-xr-x
bin2bcd_16.v
3588
log
stats
plain
-rwxr-xr-x
c5_pin_model_dump.txt
4875
log
stats
plain
-rwxr-xr-x
clktick_16.v
1078
log
stats
plain
d---------
db
8525
log
stats
plain
-rwxr-xr-x
delay_ram.v
9577
log
stats
plain
-rwxr-xr-x
ex16.qpf
1269
log
stats
plain
-rwxr-xr-x
ex16_top.asm.rpt
3881
log
stats
plain
-rwxr-xr-x
ex16_top.done
26
log
stats
plain
-rwxr-xr-x
ex16_top.eda.rpt
6103
log
stats
plain
-rwxr-xr-x
ex16_top.fit.rpt
311404
log
stats
plain
-rwxr-xr-x
ex16_top.fit.smsg
482
log
stats
plain
-rwxr-xr-x
ex16_top.fit.summary
681
log
stats
plain
-rwxr-xr-x
ex16_top.flow.rpt
8588
log
stats
plain
-rwxr-xr-x
ex16_top.jdi
227
log
stats
plain
-rwxr-xr-x
ex16_top.map.rpt
39893
log
stats
plain
-rwxr-xr-x
ex16_top.map.summary
524
log
stats
plain
-rwxr-xr-x
ex16_top.pin
105804
log
stats
plain
-rwxr-xr-x
ex16_top.qsf
14948
log
stats
plain
-rwxr-xr-x
ex16_top.qws
2331
log
stats
plain
-rwxr-xr-x
ex16_top.sdc
71
log
stats
plain
-rwxr-xr-x
ex16_top.sld
21
log
stats
plain
-rwxr-xr-x
ex16_top.sof
6690320
log
stats
plain
-rwxr-xr-x
ex16_top.sta.rpt
142654
log
stats
plain
-rwxr-xr-x
ex16_top.sta.summary
1233
log
stats
plain
-rwxr-xr-x
ex16_top.v
2190
log
stats
plain
d---------
greybox_tmp
40
log
stats
plain
-rwxr-xr-x
hex_to_7seg.v
1135
log
stats
plain
d---------
incremental_db
80
log
stats
plain
-rwxr-xr-x
mult4.v
693
log
stats
plain
-rwxr-xr-x
multiply_k.v
4404
log
stats
plain
-rwxr-xr-x
pulse_gen.v
1051
log
stats
plain
-rwxr-xr-x
pwm.v
566
log
stats
plain
d---------
simulation
/
modelsim
35
log
stats
plain
-rwxr-xr-x
spi2adc.v
4813
log
stats
plain
-rwxr-xr-x
spi2dac.v
4082
log
stats
plain