index
:
VerilogCoursework
master
Unnamed repository; edit this file 'description' to name the repository.
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
part_4
/
ex16
/
simulation
/
modelsim
/
top.sft
blob: f324fea82ad63f56a1cf15a83fcd35b84c895b12 (
plain
)
1
set tool_name "ModelSim-Altera (Verilog)"