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--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=8192 lpm_widthad=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr wreq
--VERSION_BEGIN 16.0 cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ VERSION_END
-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
FUNCTION cntr_di7 (aclr, clock, cnt_en, sclr, updown)
RETURNS ( q[12..0]);
--synthesis_resources = lut 13 reg 15
SUBDESIGN a_fefifo_4be
(
aclr : input;
clock : input;
empty : output;
full : output;
rreq : input;
sclr : input;
wreq : input;
)
VARIABLE
b_full : dffe;
b_non_empty : dffe;
count_usedw : cntr_di7;
equal_af1w[12..0] : WIRE;
equal_one[12..0] : WIRE;
is_almost_empty0 : WIRE;
is_almost_empty1 : WIRE;
is_almost_empty10 : WIRE;
is_almost_empty11 : WIRE;
is_almost_empty12 : WIRE;
is_almost_empty2 : WIRE;
is_almost_empty3 : WIRE;
is_almost_empty4 : WIRE;
is_almost_empty5 : WIRE;
is_almost_empty6 : WIRE;
is_almost_empty7 : WIRE;
is_almost_empty8 : WIRE;
is_almost_empty9 : WIRE;
is_almost_full0 : WIRE;
is_almost_full1 : WIRE;
is_almost_full10 : WIRE;
is_almost_full11 : WIRE;
is_almost_full12 : WIRE;
is_almost_full2 : WIRE;
is_almost_full3 : WIRE;
is_almost_full4 : WIRE;
is_almost_full5 : WIRE;
is_almost_full6 : WIRE;
is_almost_full7 : WIRE;
is_almost_full8 : WIRE;
is_almost_full9 : WIRE;
usedw[12..0] : WIRE;
valid_rreq : WIRE;
valid_wreq : WIRE;
BEGIN
b_full.clk = clock;
b_full.clrn = (! aclr);
b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full12 & wreq) & (! rreq)))));
b_non_empty.clk = clock;
b_non_empty.clrn = (! aclr);
b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty12 & rreq) & (! wreq))))));
count_usedw.aclr = aclr;
count_usedw.clock = clock;
count_usedw.cnt_en = (valid_wreq $ valid_rreq);
count_usedw.sclr = sclr;
count_usedw.updown = valid_wreq;
empty = (! b_non_empty.q);
equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0");
equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"0");
full = b_full.q;
is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]);
is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0);
is_almost_empty10 = ((usedw[10..10] $ equal_one[10..10]) & is_almost_empty9);
is_almost_empty11 = ((usedw[11..11] $ equal_one[11..11]) & is_almost_empty10);
is_almost_empty12 = ((usedw[12..12] $ equal_one[12..12]) & is_almost_empty11);
is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1);
is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2);
is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3);
is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4);
is_almost_empty6 = ((usedw[6..6] $ equal_one[6..6]) & is_almost_empty5);
is_almost_empty7 = ((usedw[7..7] $ equal_one[7..7]) & is_almost_empty6);
is_almost_empty8 = ((usedw[8..8] $ equal_one[8..8]) & is_almost_empty7);
is_almost_empty9 = ((usedw[9..9] $ equal_one[9..9]) & is_almost_empty8);
is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]);
is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0);
is_almost_full10 = ((usedw[10..10] $ equal_af1w[10..10]) & is_almost_full9);
is_almost_full11 = ((usedw[11..11] $ equal_af1w[11..11]) & is_almost_full10);
is_almost_full12 = ((usedw[12..12] $ equal_af1w[12..12]) & is_almost_full11);
is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1);
is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2);
is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3);
is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4);
is_almost_full6 = ((usedw[6..6] $ equal_af1w[6..6]) & is_almost_full5);
is_almost_full7 = ((usedw[7..7] $ equal_af1w[7..7]) & is_almost_full6);
is_almost_full8 = ((usedw[8..8] $ equal_af1w[8..8]) & is_almost_full7);
is_almost_full9 = ((usedw[9..9] $ equal_af1w[9..9]) & is_almost_full8);
usedw[] = count_usedw.q[];
valid_rreq = (rreq & b_non_empty.q);
valid_wreq = (wreq & (! b_full.q));
END;
--VALID FILE
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