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--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=13 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data full q rreq sclr wreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
FUNCTION a_fefifo_4be (aclr, clock, rreq, sclr, wreq)
RETURNS ( empty, full);
FUNCTION altsyncram_44t1 (address_a[12..0], address_b[12..0], clock0, clock1, clocken1, data_a[9..0], wren_a)
RETURNS ( q_b[9..0]);
FUNCTION cntr_1ib (aclr, clock, cnt_en, sclr)
RETURNS ( q[12..0]);
--synthesis_resources = lut 39 M10K 10 reg 41
SUBDESIGN a_dpfifo_br81
(
clock : input;
data[9..0] : input;
full : output;
q[9..0] : output;
rreq : input;
sclr : input;
wreq : input;
)
VARIABLE
fifo_state : a_fefifo_4be;
FIFOram : altsyncram_44t1;
rd_ptr_count : cntr_1ib;
wr_ptr : cntr_1ib;
aclr : NODE;
rd_ptr[12..0] : WIRE;
valid_rreq : WIRE;
valid_wreq : WIRE;
BEGIN
fifo_state.aclr = aclr;
fifo_state.clock = clock;
fifo_state.rreq = rreq;
fifo_state.sclr = sclr;
fifo_state.wreq = wreq;
FIFOram.address_a[] = wr_ptr.q[];
FIFOram.address_b[] = ((! sclr) & rd_ptr[]);
FIFOram.clock0 = clock;
FIFOram.clock1 = clock;
FIFOram.clocken1 = (valid_rreq # sclr);
FIFOram.data_a[] = data[];
FIFOram.wren_a = valid_wreq;
rd_ptr_count.aclr = aclr;
rd_ptr_count.clock = clock;
rd_ptr_count.cnt_en = valid_rreq;
rd_ptr_count.sclr = sclr;
wr_ptr.aclr = aclr;
wr_ptr.clock = clock;
wr_ptr.cnt_en = valid_wreq;
wr_ptr.sclr = sclr;
aclr = GND;
full = fifo_state.full;
q[] = FIFOram.q_b[];
rd_ptr[] = rd_ptr_count.q[];
valid_rreq = (rreq & (! fifo_state.empty));
valid_wreq = (wreq & (! fifo_state.full));
END;
--VALID FILE
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