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--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone V" LPM_NUMWORDS=8192 LPM_SHOWAHEAD="OFF" LPM_WIDTH=10 LPM_WIDTHU=13 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data full q rdreq wrreq ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone V" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 16.0 cbx_altdpram 2016:04:27:18:05:34:SJ cbx_altera_syncram 2016:04:27:18:05:34:SJ cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_fifo_common 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_scfifo 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, the Altera Quartus Prime License Agreement,
-- the Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of programming logic
-- devices manufactured by Altera and sold by Altera or its
-- authorized distributors. Please refer to the applicable
-- agreement for further details.
FUNCTION a_dpfifo_br81 (clock, data[9..0], rreq, sclr, wreq)
RETURNS ( full, q[9..0]);
--synthesis_resources = lut 39 M10K 10 reg 41
SUBDESIGN scfifo_4l81
(
clock : input;
data[9..0] : input;
full : output;
q[9..0] : output;
rdreq : input;
wrreq : input;
)
VARIABLE
dpfifo : a_dpfifo_br81;
sclr : NODE;
BEGIN
dpfifo.clock = clock;
dpfifo.data[] = data[];
dpfifo.rreq = rdreq;
dpfifo.sclr = sclr;
dpfifo.wreq = wrreq;
full = dpfifo.full;
q[] = dpfifo.q[];
sclr = GND;
END;
--VALID FILE
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