diff options
Diffstat (limited to 'dot_product/catapult.log')
| -rw-r--r-- | dot_product/catapult.log | 677 |
1 files changed, 677 insertions, 0 deletions
diff --git a/dot_product/catapult.log b/dot_product/catapult.log new file mode 100644 index 0000000..1a6b0b3 --- /dev/null +++ b/dot_product/catapult.log @@ -0,0 +1,677 @@ +// Catapult University Version 2011a.126 (Production Release) Wed Aug 8 00:52:07 PDT 2012 +// +// Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved. +// UNPUBLISHED, LICENSED SOFTWARE. +// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE +// PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS +// +// Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686 +// +// Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, +// DesignPad v2.78_0.0 +// +// This version may only be used for academic purposes. Some optimizations +// are disabled, so results obtained from this version may be sub-optimal. +// +// Start time Tue Mar 01 14:25:21 2016 +# ------------------------------------------------- +# Logging session transcript to file "C:\Users\mg3115\AppData\Local\Temp\log682424fa020.0" +# Loading options from registry. +project load {C:/Catapult C/dot_product/dot_product.ccs} +# Moving session transcript to file "C:\Catapult C\dot_product\catapult.log" +# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_busdefs.lib' [mgc_busdefs]... (LIB-49) +# Reading component library '$MGC_HOME\pkgs\siflibs\stdops.lib' [STDOPS]... (LIB-49) +# Reading component library '$MGC_HOME\pkgs\siflibs\mgc_ioport.lib' [mgc_ioport]... (LIB-49) +# Reading component library '$MGC_HOME\pkgs\ccs_altera\Altera_accel_CycloneIII.lib' [Altera_accel_CycloneIII]... (LIB-49) +# Reading component library '$MGC_HOME\pkgs\siflibs\psr2010a_up2\mgc_Altera-Cyclone-III-6_beh_psr.lib' [mgc_Altera-Cyclone-III-6_beh_psr]... (LIB-49) +flow run /SCVerify/launch_make ././scverify/Verify_orig_cxx_osci.mk {} SIMTOOL=osci sim +# Making '././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim' +# C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "NUL:" (BASIC-15) +# "============================================" +# "Creating simulation directory 'scverify\orig_cxx_osci'" +# mkdir scverify\orig_cxx_osci +# "============================================" +# "Compiling C++ file: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp" +# "c:\PROGRA~2\MICROS~4.0\VC\bin\cl.exe" -DCCS_DUT_SYSC -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=dot_product /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION /D"WIN32" /D"_DEBUG" /D"_CONSOLE" /D"NOGDI" /D"_MBCS" /D"_CRT_SECURE_NO_DEPRECATE" /EHsc /RTCs /MTd /FD /W3 /Z7 /vmg /I"C:/Program Files/Microsoft Platform SDK/Include" /I. /I../.. /I. /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/src /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/siflibs /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING /c /Tp ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp /Foscverify/orig_cxx_osci/dot_product.cpp.cxxts.obj +# Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 15.00.30729.01 for 80x86 +# Copyright (C) Microsoft Corporation. All rights reserved. +# +# dot_product.cpp +# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(26) : warning C4068: unknown pragma +# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31) : warning C4102: 'MAC' : unreferenced label +# "============================================" +# "Compiling C++ file: ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp" +# "c:\PROGRA~2\MICROS~4.0\VC\bin\cl.exe" -DCCS_DUT_SYSC -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DTOP_HDL_ENTITY=dot_product /W3 -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION /D"WIN32" /D"_DEBUG" /D"_CONSOLE" /D"NOGDI" /D"_MBCS" /D"_CRT_SECURE_NO_DEPRECATE" /EHsc /RTCs /MTd /FD /W3 /Z7 /vmg /I"C:/Program Files/Microsoft Platform SDK/Include" /I. /I../.. /I. /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/include /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/src /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/siflibs /IC:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING /c /Tp ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp /Foscverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj +# Microsoft (R) 32-bit C/C++ Optimizing Compiler Version 15.00.30729.01 for 80x86 +# Copyright (C) Microsoft Corporation. All rights reserved. +# +# tb_dot_product.cpp +# ../../../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp(39) : warning C4244: '+=' : conversion from 'Slong' to 'int', possible loss of data +# "============================================" +# "Linking executable" +# "c:\PROGRA~2\MICROS~4.0\VC\bin\link.exe" /SUBSYSTEM:CONSOLE /DEBUG /DYNAMICBASE:NO /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/Windows_NT/msvc /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib /LIBPATH:C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/shared/lib/Windows_NT/msvc scverify/orig_cxx_osci/dot_product.cpp.cxxts.obj scverify/orig_cxx_osci/tb_dot_product.cpp.cxxts.obj libsystemc.lib /out:scverify/orig_cxx_osci/scverify_top.exe +# Microsoft (R) Incremental Linker Version 9.00.30729.01 +# Copyright (C) Microsoft Corporation. All rights reserved. +# +# C:/PROGRA~1/CALYPT~1/CATAPU~1.126/Mgc_home/bin/make -f ././scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14) +# chdir ..\..& dot_product\dot_product.v1\scverify\orig_cxx_osci\scverify_top.exe +# Inputs: A = 1, B = 5 +# Inputs: A = 2, B = 4 +# Inputs: A = 3, B = 3 +# Inputs: A = 4, B = 2 +# Inputs: A = 5, B = 1 +# Design output : 35 +# Expected output: 35 +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v1' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 33, Real ops = 6, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 4) (SOL-10) +# Design 'dot_product' contains '8' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v1': elapsed time 0.38 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v1' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Prescheduled LOOP 'MAC' (1 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 7 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 426.23, 0.00, 426.23 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v1': elapsed time 0.06 seconds, memory usage 153804kB, peak memory usage 166132kB (SOL-9) +flow run /Schedule/view ./schedule.gnt +flow run /Schedule/view ./schedule.gnt +go compile +directive set /dot_product/core/main/MAC -UNROLL yes +# Info: Branching solution 'dot_product.v2' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/MAC/UNROLL yes +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v2' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v2': elapsed time 0.69 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v2' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v2': elapsed time 0.05 seconds, memory usage 162000kB, peak memory usage 170216kB (SOL-9) +go compile +directive set /dot_product/core/main/MAC -UNROLL no +# Info: Branching solution 'dot_product.v3' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/MAC/UNROLL no +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1 +# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1 +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v3' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10) +# Design 'dot_product' contains '12' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v3': elapsed time 1.08 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v3' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v3': elapsed time 0.06 seconds, memory usage 166268kB, peak memory usage 178592kB (SOL-9) +go compile +directive set /dot_product/core/main/MAC -UNROLL yes +# Info: Branching solution 'dot_product.v4' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/MAC/UNROLL yes +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0 +# /dot_product/core/main/PIPELINE_INIT_INTERVAL 0 +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v4' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v4': elapsed time 1.47 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v4' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1358.03, 0.00, 1358.03 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 2, Area (Datapath, Register, Total) = 1027.78, 0.00, 1027.78 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 3, Area (Datapath, Register, Total) = 697.53, 0.00, 697.53 (CRAAS-10) +# Info: Optimized LOOP 'main': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-10) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v4': elapsed time 0.06 seconds, memory usage 169372kB, peak memory usage 178592kB (SOL-9) +go compile +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1 +# Info: Branching solution 'dot_product.v5' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1 +directive set /dot_product/core/main/MAC -UNROLL no +# /dot_product/core/main/MAC/UNROLL no +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v5' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 17, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 17, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 49, Real ops = 11, Vars = 22) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 27, Real ops = 10, Vars = 7) (SOL-10) +# Design 'dot_product' contains '12' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v5': elapsed time 1.79 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v5' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 434.25, 0.00, 434.25 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v5': elapsed time 0.06 seconds, memory usage 172008kB, peak memory usage 184332kB (SOL-9) +go compile +directive set /dot_product/input_b -STREAM 8 +# Info: Branching solution 'dot_product.v6' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/input_b/STREAM 8 +directive set /dot_product/input_b -WORD_WIDTH 8 +# /dot_product/input_b/WORD_WIDTH 8 +directive set /dot_product/core/main/MAC -UNROLL yes +# /dot_product/core/main/MAC/UNROLL yes +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v6' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 23, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 19, Real ops = 7, Vars = 7) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 24, Real ops = 7, Vars = 4) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 19, Real ops = 7, Vars = 1) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v6': elapsed time 2.09 seconds, memory usage 174832kB, peak memory usage 184332kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v6' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Error: insufficient resources 'mgc_ioport.mgc_in_wire(2,8)' to schedule 'core'. 5 are needed, but only 1 instances are available (SCHD-4) +# Error: Design 'dot_product' could not schedule partition '/dot_product/core' - resource competition +go compile +directive set /dot_product/input_b -WORD_WIDTH 40 +# Info: Branching solution 'dot_product.v7' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/input_b/WORD_WIDTH 40 +directive set /dot_product/input_b -STREAM 0 +# /dot_product/input_b/STREAM 0 +go allocate +# Info: Starting transformation 'architect' on solution 'dot_product.v7' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 40). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 28, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 20, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 30, Real ops = 7, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 20, Real ops = 7, Vars = 2) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v7': elapsed time 2.60 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v7' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 1, Area (Datapath, Register, Total) = 1688.28, 0.00, 1688.28 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v7': elapsed time 0.06 seconds, memory usage 176692kB, peak memory usage 184908kB (SOL-9) +go compile +directive set /dot_product/input_a -WORD_WIDTH 8 +# Info: Branching solution 'dot_product.v8' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/input_a/WORD_WIDTH 8 +directive set /dot_product/input_a -STREAM 8 +# /dot_product/input_a/STREAM 8 +directive set /dot_product/input_b -WORD_WIDTH 8 +# /dot_product/input_b/WORD_WIDTH 8 +directive set /dot_product/input_b -STREAM 8 +# /dot_product/input_b/STREAM 8 +options set Output OutputVHDL false +# false +options set Output OutputVerilog true +# true +go extract +# Info: Starting transformation 'architect' on solution 'dot_product.v8' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v8': elapsed time 2.79 seconds, memory usage 179500kB, peak memory usage 187716kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v8' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Error: insufficient resources 'mgc_ioport.mgc_in_wire(1,8)' to schedule 'core'. 5 are needed, but only 1 instances are available (SCHD-4) +# Error: Design 'dot_product' could not schedule partition '/dot_product/core' - resource competition +go compile +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0 +# Info: Branching solution 'dot_product.v9' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/PIPELINE_INIT_INTERVAL 0 +directive set /dot_product/core/main/MAC -UNROLL no +# /dot_product/core/main/MAC/UNROLL no +directive set /dot_product/core/main/MAC -UNROLL yes +# /dot_product/core/main/MAC/UNROLL yes +go extract +# Info: Starting transformation 'architect' on solution 'dot_product.v9' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is being fully unrolled (5 times). (LOOP-7) +# Info: Optimizing partition '/dot_product/core': (Total ops = 59, Real ops = 26, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 18, Real ops = 7, Vars = 6) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 18, Real ops = 7, Vars = 0) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v9': elapsed time 3.24 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v9' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 367.28, 0.00, 367.28 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v9': elapsed time 0.08 seconds, memory usage 182072kB, peak memory usage 190288kB (SOL-9) +# Info: Starting transformation 'schedule' on solution 'dot_product.v9' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3) +# Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3) +# Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3) +# Info: Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 20) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 27, Real ops = 10, Vars = 10) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 21, Real ops = 10, Vars = 4) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 10, Real ops = 10, Vars = 4) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 28, Real ops = 10, Vars = 19) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 16, Real ops = 10, Vars = 10) (SOL-10) +# Report written to file 'cycle.rpt' +# Netlist written to file 'cycle.v' (NET-4) +# Error: Streamed resource 'input_a:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en). +# Error: Streamed resource 'input_b:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en). +# Info: Wrote wave database file to C:/CATAPU~1/dot_product/dot_product/dot_product.v9/scverify/ccs_wave_signals.dat +# Makefile for Cycle Verilog output 'cycle.v' vs Untimed C++ written to file 'scverify/Verify_cycle_v_msim.mk' +# Info: Completed transformation 'schedule' on solution 'dot_product.v9': elapsed time 1.08 seconds, memory usage 183844kB, peak memory usage 190288kB (SOL-9) +# Info: Starting transformation 'dpfsm' on solution 'dot_product.v9' (SOL-8) +# Performing FSM extraction... (FSM-1) +# Info: Optimizing partition '/dot_product': (Total ops = 56, Real ops = 16, Vars = 50) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 44, Real ops = 16, Vars = 41) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 46, Real ops = 13, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 13, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 38, Real ops = 10, Vars = 25) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 26, Real ops = 10, Vars = 16) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Completed transformation 'dpfsm' on solution 'dot_product.v9': elapsed time 0.09 seconds, memory usage 184104kB, peak memory usage 190368kB (SOL-9) +# Info: Starting transformation 'extract' on solution 'dot_product.v9' (SOL-8) +# Shared Operations MAC:acc#5,MAC:acc#6,MAC:acc on resource MAC:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8):mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) (ASG-3) +# Info: Optimizing partition '/dot_product': (Total ops = 46, Real ops = 11, Vars = 36) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 34, Real ops = 11, Vars = 27) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Netlist written to file 'schematic.nlv' (NET-4) +# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 11, Vars = 33) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 11, Vars = 24) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 42, Real ops = 10, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 30, Real ops = 10, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 29, Real ops = 11, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 40, Real ops = 11, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 28, Real ops = 11, Vars = 17) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm': (Total ops = 6, Real ops = 2, Vars = 5) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/dot_product:core:fsm/dot_product:core:fsm': (Total ops = 1, Real ops = 1, Vars = 1) (SOL-10) +# Report written to file 'rtl.rpt' +# Netlist written to file 'rtl.v' (NET-4) +# generate concat +# order file name is: rtl.v_order.txt +# Add dependent file: ./rtl_mgc_ioport.v +# Add dependent file: ./rtl_mgc_ioport_v2001.v +# Add dependent file: ./rtl.v +# Finished writing concatenated file: C:/Catapult C/dot_product/dot_product/dot_product.v9/concat_rtl.v +# Synthesis timing script written to file './rtl.v.psr_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'rtl.v.psr' +# Makefile for RTL Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_rtl_v_msim.mk' +# Synthesis timing script written to file './scverify/mapped.psrv_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'mapped.psrv' +# Makefile for Mapped Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_mapped_v_msim.mk' +# Synthesis timing script written to file './scverify/gate.psrv_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'gate.psrv' +# Makefile for Gate Verilog output 'gate.v' vs Untimed C++ written to file 'scverify/Verify_gate_v_msim.mk' +# Info: Completed transformation 'extract' on solution 'dot_product.v9': elapsed time 2.70 seconds, memory usage 188780kB, peak memory usage 192380kB (SOL-9) +go instance +flow run /Schematic/view ./schematic.nlv -state rtl +flow run /Schematic/view ./schematic.nlv -state rtl +flow run /Schematic/view ./schematic.nlv -state rtl +flow run /Schematic/view ./schematic.nlv -state datapath +flow run /Schematic/view ./schematic.nlv -state criticalpath +flow run /Schematic/view ./schematic.nlv -state datapath +flow run /Schematic/view ./schematic.nlv -state rtl +go extract +go compile +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 1 +# Info: Branching solution 'dot_product.v10' at state 'compile' (PRJ-2) +# Makefile for Original Design + Testbench written to file 'scverify/Verify_orig_cxx_osci.mk' +# /dot_product/core/main/PIPELINE_INIT_INTERVAL 1 +directive set /dot_product/core/main/MAC -UNROLL no +# /dot_product/core/main/MAC/UNROLL no +go extract +# Info: Starting transformation 'architect' on solution 'dot_product.v10' (SOL-8) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(31): Loop '/dot_product/core/MAC' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Loop '/dot_product/core/main' is left rolled. (LOOP-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_a:rsc' (from var: input_a) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'input_b:rsc' (from var: input_b) mapped to 'mgc_ioport.mgc_in_wire' (size: 8). (MEM-2) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): I/O-Port inferred - resource 'output:rsc' (from var: output) mapped to 'mgc_ioport.mgc_out_stdreg' (size: 8). (MEM-2) +# Info: Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 15, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 13, Real ops = 6, Vars = 2) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 13, Real ops = 6, Vars = 8) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 16, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 15, Real ops = 6, Vars = 3) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 45, Real ops = 11, Vars = 22) (SOL-10) +# Info: Optimizing partition '/dot_product/core': (Total ops = 23, Real ops = 10, Vars = 6) (SOL-10) +# Design 'dot_product' contains '10' real operations. (SOL-11) +# Info: Completed transformation 'architect' on solution 'dot_product.v10': elapsed time 3.62 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9) +# Info: Starting transformation 'allocate' on solution 'dot_product.v10' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Info: Select qualified components for data operations ... (CRAAS-3) +# Info: Apply resource constraints on data operations ... (CRAAS-4) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled LOOP 'main' (2 c-steps) (SCHD-7) +# $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp(27): Prescheduled SEQUENTIAL 'core' (total length 2 c-steps) (SCHD-8) +# Info: Initial schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-11) +# At least one feasible schedule exists. (CRAAS-9) +# Info: Final schedule of SEQUENTIAL 'core': Latency = 5, Area (Datapath, Register, Total) = 356.83, 0.00, 356.83 (CRAAS-12) +# Resource allocation and scheduling done. (CRAAS-2) +# Netlist written to file 'schedule.gnt' (NET-4) +# Info: Completed transformation 'allocate' on solution 'dot_product.v10': elapsed time 0.06 seconds, memory usage 192028kB, peak memory usage 204352kB (SOL-9) +# Info: Starting transformation 'schedule' on solution 'dot_product.v10' (SOL-8) +# Performing concurrent resource allocation and scheduling on '/dot_product/core' (CRAAS-1) +# Global signal 'input_a:rsc.z' added to design 'dot_product' for component 'input_a:rsc:mgc_in_wire' (LIB-3) +# Global signal 'input_b:rsc.z' added to design 'dot_product' for component 'input_b:rsc:mgc_in_wire' (LIB-3) +# Global signal 'output:rsc.z' added to design 'dot_product' for component 'output:rsc:mgc_out_stdreg' (LIB-3) +# Info: Optimizing partition '/dot_product': (Total ops = 49, Real ops = 11, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 36, Real ops = 10, Vars = 16) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 30, Real ops = 10, Vars = 10) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core/core': (Total ops = 17, Real ops = 10, Vars = 4) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 10, Vars = 19) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 10, Vars = 10) (SOL-10) +# Report written to file 'cycle.rpt' +# Netlist written to file 'cycle.v' (NET-4) +# Error: Streamed resource 'input_a:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en). +# Error: Streamed resource 'input_b:rsc' must be mapped to an interface synthesis component having an enable handshake signal (i.e. mgc_in_wire_en/mgc_out_stdreg_en). +# Info: Wrote wave database file to C:/CATAPU~1/dot_product/dot_product/dot_product.v10/scverify/ccs_wave_signals.dat +# Makefile for Cycle Verilog output 'cycle.v' vs Untimed C++ written to file 'scverify/Verify_cycle_v_msim.mk' +# Info: Completed transformation 'schedule' on solution 'dot_product.v10': elapsed time 1.12 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9) +# Info: Starting transformation 'dpfsm' on solution 'dot_product.v10' (SOL-8) +# Performing FSM extraction... (FSM-1) +# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 13, Vars = 35) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 13, Vars = 26) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 43, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 31, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 12) (SOL-10) +# Info: Completed transformation 'dpfsm' on solution 'dot_product.v10': elapsed time 0.08 seconds, memory usage 193784kB, peak memory usage 204352kB (SOL-9) +# Info: Starting transformation 'extract' on solution 'dot_product.v10' (SOL-8) +# Warning: Reassigned operation MAC:acc:mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) to mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,0,3) (ASG-1) +# Info: Optimizing partition '/dot_product': (Total ops = 35, Real ops = 14, Vars = 31) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 23, Real ops = 14, Vars = 22) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10) +# Netlist written to file 'schematic.nlv' (NET-4) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 32) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 23) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Info: Optimizing partition '/dot_product': (Total ops = 36, Real ops = 14, Vars = 21) (SOL-10) +# Info: Optimizing partition '/dot_product/dot_product:core': (Total ops = 24, Real ops = 14, Vars = 12) (SOL-10) +# Report written to file 'rtl.rpt' +# Netlist written to file 'rtl.v' (NET-4) +# generate concat +# order file name is: rtl.v_order.txt +# Add dependent file: ./rtl_mgc_ioport.v +# Add dependent file: ./rtl_mgc_ioport_v2001.v +# Add dependent file: ./rtl.v +# Finished writing concatenated file: C:/Catapult C/dot_product/dot_product/dot_product.v10/concat_rtl.v +# Synthesis timing script written to file './rtl.v.psr_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'rtl.v.psr' +# Makefile for RTL Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_rtl_v_msim.mk' +# Synthesis timing script written to file './scverify/mapped.psrv_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'mapped.psrv' +# Makefile for Mapped Verilog output 'rtl.v' vs Untimed C++ written to file 'scverify/Verify_mapped_v_msim.mk' +# Synthesis timing script written to file './scverify/gate.psrv_timing' +# IO timing constraints written to synthesis script file +# Synthesis script written to file 'gate.psrv' +# Makefile for Gate Verilog output 'gate.v' vs Untimed C++ written to file 'scverify/Verify_gate_v_msim.mk' +# Info: Completed transformation 'extract' on solution 'dot_product.v10': elapsed time 2.64 seconds, memory usage 194292kB, peak memory usage 204352kB (SOL-9) +go instance +flow run /Schematic/view ./schematic.nlv -state rtl +go extract +go instance +flow run /Schematic/view ./schematic.nlv -state rtl |