diff options
Diffstat (limited to 'dot_product/dot_product/dot_product.v1/schedule.gnt')
| -rw-r--r-- | dot_product/dot_product/dot_product.v1/schedule.gnt | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/dot_product/dot_product/dot_product.v1/schedule.gnt b/dot_product/dot_product/dot_product.v1/schedule.gnt new file mode 100644 index 0000000..922430b --- /dev/null +++ b/dot_product/dot_product/dot_product.v1/schedule.gnt @@ -0,0 +1,39 @@ +set a(0-11) {NAME acc:asn(acc) TYPE ASSIGN PAR 0-10 XREFS 362 LOC {0 1.0 0 1.0 0 1.0 1 1.0} PREDS {{772 0 0-13 {}}} SUCCS {{258 0 0-13 {}}} CYCLES {}} +set a(0-12) {NAME MAC:asn(i) TYPE ASSIGN PAR 0-10 XREFS 363 LOC {0 1.0 0 1.0 0 1.0 1 1.0} PREDS {{772 0 0-13 {}}} SUCCS {{259 0 0-13 {}}} CYCLES {}} +set a(0-14) {LIBRARY mgc_ioport MODULE mgc_in_wire(1,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_a:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-13 XREFS 364 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {} SUCCS {{258 0 0-17 {}} {258 0 0-18 {}} {258 0 0-19 {}} {258 0 0-20 {}} {258 0 0-21 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-15) {LIBRARY mgc_ioport MODULE mgc_in_wire(2,40) AREA_SCORE 0.00 QUANTITY 1 NAME MAC:io_read(input_b:rsc.d) TYPE {I/O_READ VAR} DELAY {0.00 ns} PAR 0-13 XREFS 365 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {} SUCCS {{258 0 0-24 {}} {258 0 0-25 {}} {258 0 0-26 {}} {258 0 0-27 {}} {258 0 0-28 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-16) {NAME MAC:asn TYPE ASSIGN PAR 0-13 XREFS 366 LOC {0 1.0 1 0.92730525 1 0.92730525 1 0.92730525} PREDS {{774 0 0-40 {}}} SUCCS {{258 0 0-32 {}} {130 0 0-39 {}} {256 0 0-40 {}}} CYCLES {}} +set a(0-17) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt) TYPE READSLICE PAR 0-13 XREFS 367 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-18) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#1 TYPE READSLICE PAR 0-13 XREFS 368 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-19) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#2 TYPE READSLICE PAR 0-13 XREFS 369 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-20) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#3 TYPE READSLICE PAR 0-13 XREFS 370 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-21) {NAME MAC:slc(MAC:io_read(input_a:rsc.d).sdt)#4 TYPE READSLICE PAR 0-13 XREFS 371 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-14 {}}} SUCCS {{258 0 0-23 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-22) {NAME MAC:asn#4 TYPE ASSIGN PAR 0-13 XREFS 372 LOC {0 1.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-23 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}} +set a(0-23) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-13 XREFS 373 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-21 {}} {258 0 0-20 {}} {258 0 0-19 {}} {258 0 0-18 {}} {258 0 0-17 {}} {259 0 0-22 {}}} SUCCS {{258 0 0-31 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-24) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt) TYPE READSLICE PAR 0-13 XREFS 374 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-25) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#1 TYPE READSLICE PAR 0-13 XREFS 375 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-26) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#2 TYPE READSLICE PAR 0-13 XREFS 376 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-27) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#3 TYPE READSLICE PAR 0-13 XREFS 377 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-28) {NAME MAC:slc(MAC:io_read(input_b:rsc.d).sdt)#4 TYPE READSLICE PAR 0-13 XREFS 378 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{258 0 0-15 {}}} SUCCS {{258 0 0-30 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-29) {NAME MAC:asn#5 TYPE ASSIGN PAR 0-13 XREFS 379 LOC {0 1.0 1 0.667109025 1 0.667109025 1 0.667109025} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-30 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}} +set a(0-30) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mux(8,3,8) AREA_SCORE 38.71 QUANTITY 2 NAME MAC:mux#1 TYPE MUX DELAY {1.50 ns} LIBRARY_DELAY {1.50 ns} PAR 0-13 XREFS 380 LOC {1 0.0 1 0.667109025 1 0.667109025 1 0.7611039625 1 0.7611039625} PREDS {{258 0 0-28 {}} {258 0 0-27 {}} {258 0 0-26 {}} {258 0 0-25 {}} {258 0 0-24 {}} {259 0 0-29 {}}} SUCCS {{259 0 0-31 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-31) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_mul(8,0,8,0,8) AREA_SCORE 330.25 QUANTITY 1 NAME MAC:mul TYPE MUL DELAY {2.66 ns} LIBRARY_DELAY {2.66 ns} PAR 0-13 XREFS 381 LOC {1 0.093995 1 0.761104025 1 0.761104025 1 0.9273051907433434 1 0.9273051907433434} PREDS {{258 0 0-23 {}} {259 0 0-30 {}}} SUCCS {{259 0 0-32 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-32) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(8,0,8,0,8) AREA_SCORE 9.26 QUANTITY 1 NAME MAC:acc#3 TYPE ACCU DELAY {1.16 ns} LIBRARY_DELAY {1.16 ns} PAR 0-13 XREFS 382 LOC {1 0.260196225 1 0.92730525 1 0.92730525 1 0.9999999527684257 1 0.9999999527684257} PREDS {{258 0 0-16 {}} {259 0 0-31 {}}} SUCCS {{130 0 0-39 {}} {258 0 0-40 {}}} CYCLES {}} +set a(0-33) {NAME MAC:asn#6 TYPE ASSIGN PAR 0-13 XREFS 383 LOC {0 1.0 1 0.898700525 1 0.898700525 1 0.898700525} PREDS {{774 0 0-41 {}}} SUCCS {{259 0 0-34 {}} {130 0 0-39 {}} {256 0 0-41 {}}} CYCLES {}} +set a(0-34) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(3,0,2,1,3) AREA_SCORE 4.00 QUANTITY 1 NAME MAC:acc#4 TYPE ACCU DELAY {0.76 ns} LIBRARY_DELAY {0.76 ns} PAR 0-13 XREFS 384 LOC {1 0.0 1 0.898700525 1 0.898700525 1 0.9464762270241717 1 0.9464762270241717} PREDS {{259 0 0-33 {}}} SUCCS {{259 0 0-35 {}} {130 0 0-39 {}} {258 0 0-41 {}}} CYCLES {}} +set a(0-35) {NAME MAC:asn#3 TYPE ASSIGN PAR 0-13 XREFS 385 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 0.946476275} PREDS {{259 0 0-34 {}}} SUCCS {{259 0 0-36 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-36) {LIBRARY mgc_Altera-Cyclone-III-6_beh_psr MODULE mgc_add(4,0,3,0,4) AREA_SCORE 5.30 QUANTITY 1 NAME MAC:acc TYPE ACCU DELAY {0.86 ns} LIBRARY_DELAY {0.86 ns} PAR 0-13 XREFS 386 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 0.9999999399089293 1 0.9999999399089293} PREDS {{259 0 0-35 {}}} SUCCS {{259 0 0-37 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-37) {NAME MAC:slc TYPE READSLICE PAR 0-13 XREFS 387 LOC {1 0.101299475 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-36 {}}} SUCCS {{259 0 0-38 {}} {130 0 0-39 {}}} CYCLES {}} +set a(0-38) {NAME MAC:not TYPE NOT PAR 0-13 XREFS 388 LOC {1 0.101299475 1 1.0 1 1.0 1 1.0} PREDS {{259 0 0-37 {}}} SUCCS {{259 0 0-39 {}}} CYCLES {}} +set a(0-39) {NAME break(MAC) TYPE TERMINATE PAR 0-13 XREFS 389 LOC {1 0.332890975 1 1.0 1 1.0 1 1.0} PREDS {{130 0 0-14 {}} {130 0 0-15 {}} {130 0 0-16 {}} {130 0 0-17 {}} {130 0 0-18 {}} {130 0 0-19 {}} {130 0 0-20 {}} {130 0 0-21 {}} {130 0 0-22 {}} {130 0 0-23 {}} {130 0 0-24 {}} {130 0 0-25 {}} {130 0 0-26 {}} {130 0 0-27 {}} {130 0 0-28 {}} {130 0 0-29 {}} {130 0 0-30 {}} {130 0 0-31 {}} {130 0 0-32 {}} {130 0 0-33 {}} {130 0 0-34 {}} {130 0 0-35 {}} {130 0 0-36 {}} {130 0 0-37 {}} {259 0 0-38 {}}} SUCCS {{129 0 0-40 {}} {128 0 0-41 {}}} CYCLES {}} +set a(0-40) {NAME MAC:asn(acc.sva) TYPE ASSIGN PAR 0-13 XREFS 390 LOC {1 0.332890975 1 1.0 1 1.0 1 1.0} PREDS {{772 0 0-40 {}} {256 0 0-16 {}} {258 0 0-32 {}} {129 0 0-39 {}}} SUCCS {{774 0 0-16 {}} {772 0 0-40 {}}} CYCLES {}} +set a(0-41) {NAME MAC:asn(i#1.sva) TYPE ASSIGN PAR 0-13 XREFS 391 LOC {1 0.04777575 1 0.946476275 1 0.946476275 1 1.0} PREDS {{128 0 0-39 {}} {772 0 0-41 {}} {256 0 0-22 {}} {256 0 0-29 {}} {256 0 0-33 {}} {258 0 0-34 {}}} SUCCS {{774 0 0-22 {}} {774 0 0-29 {}} {774 0 0-33 {}} {772 0 0-41 {}}} CYCLES {}} +set a(0-13) {CHI {0-14 0-15 0-16 0-17 0-18 0-19 0-20 0-21 0-22 0-23 0-24 0-25 0-26 0-27 0-28 0-29 0-30 0-31 0-32 0-33 0-34 0-35 0-36 0-37 0-38 0-39 0-40 0-41} ITERATIONS 5 RESET_LATENCY 0 CSTEPS 1 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 5 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 5 TOTAL_CYCLES_IN 5 TOTAL_CYCLES_UNDER 0 TOTAL_CYCLES 5 NAME MAC TYPE LOOP DELAY {120.00 ns} PAR 0-10 XREFS 392 LOC {1 1.0 1 1.0 1 1.0 1 1.0} PREDS {{258 0 0-11 {}} {259 0 0-12 {}}} SUCCS {{772 0 0-11 {}} {772 0 0-12 {}} {259 0 0-42 {}}} CYCLES {}} +set a(0-42) {LIBRARY mgc_ioport MODULE mgc_out_stdreg(3,8) AREA_SCORE 0.00 QUANTITY 1 NAME io_write(output:rsc.d) TYPE {I/O_WRITE VAR} DELAY {0.00 ns} PAR 0-10 XREFS 393 LOC {1 1.0 1 1.0 1 1.0 2 0.0 1 0.9999} PREDS {{772 0 0-42 {}} {259 0 0-13 {}}} SUCCS {{772 0 0-42 {}}} CYCLES {}} +set a(0-10) {CHI {0-11 0-12 0-13 0-42} ITERATIONS Infinite LATENCY 5 RESET_LATENCY 0 CSTEPS 2 UNROLL 0 PERIOD {20.00 ns} FULL_PERIOD {20.00 ns} THROUGHPUT_PERIOD 7 %_SHARING_ALLOC {20.0 %} PIPELINED No CYCLES_IN 2 TOTAL_CYCLES_IN 2 TOTAL_CYCLES_UNDER 5 TOTAL_CYCLES 7 NAME main TYPE LOOP DELAY {160.00 ns} PAR {} XREFS 394 LOC {0 0.0 0 0.0 0 0.0 1 0.0} PREDS {} SUCCS {} CYCLES {}} +set a(0-10-TOTALCYCLES) {7} +set a(0-10-QMOD) {mgc_ioport.mgc_in_wire(1,40) 0-14 mgc_ioport.mgc_in_wire(2,40) 0-15 mgc_Altera-Cyclone-III-6_beh_psr.mgc_mux(8,3,8) {0-23 0-30} mgc_Altera-Cyclone-III-6_beh_psr.mgc_mul(8,0,8,0,8) 0-31 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(8,0,8,0,8) 0-32 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(3,0,2,1,3) 0-34 mgc_Altera-Cyclone-III-6_beh_psr.mgc_add(4,0,3,0,4) 0-36 mgc_ioport.mgc_out_stdreg(3,8) 0-42} +set a(0-10-PROC_NAME) {core} +set a(0-10-HIER_NAME) {/dot_product/core} +set a(TOP) {0-10} + |