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Diffstat (limited to 'dot_product/dot_product/dot_product.v10/concat_rtl.v')
| -rw-r--r-- | dot_product/dot_product/dot_product.v10/concat_rtl.v | 1411 |
1 files changed, 1411 insertions, 0 deletions
diff --git a/dot_product/dot_product/dot_product.v10/concat_rtl.v b/dot_product/dot_product/dot_product.v10/concat_rtl.v new file mode 100644 index 0000000..f2b2560 --- /dev/null +++ b/dot_product/dot_product/dot_product.v10/concat_rtl.v @@ -0,0 +1,1411 @@ + +//------> ./rtl_mgc_ioport.v +//------------------------------------------------------------------ +// M G C _ I O P O R T _ C O M P S +//------------------------------------------------------------------ + +//------------------------------------------------------------------ +// M O D U L E S +//------------------------------------------------------------------ + +//------------------------------------------------------------------ +//-- INPUT ENTITIES +//------------------------------------------------------------------ + +module mgc_in_wire (d, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + output [width-1:0] d; + input [width-1:0] z; + + wire [width-1:0] d; + + assign d = z; + +endmodule + +//------------------------------------------------------------------ + +module mgc_in_wire_en (ld, d, lz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ld; + output [width-1:0] d; + output lz; + input [width-1:0] z; + + wire [width-1:0] d; + wire lz; + + assign d = z; + assign lz = ld; + +endmodule + +//------------------------------------------------------------------ + +module mgc_in_wire_wait (ld, vd, d, lz, vz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + + wire vd; + wire [width-1:0] d; + wire lz; + + assign d = z; + assign lz = ld; + assign vd = vz; + +endmodule +//------------------------------------------------------------------ + +module mgc_chan_in (ld, vd, d, lz, vz, z, size, req_size, sizez, sizelz); + + parameter integer rscid = 1; + parameter integer width = 8; + parameter integer sz_width = 8; + + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + output [sz_width-1:0] size; + input req_size; + input [sz_width-1:0] sizez; + output sizelz; + + + wire vd; + wire [width-1:0] d; + wire lz; + wire [sz_width-1:0] size; + wire sizelz; + + assign d = z; + assign lz = ld; + assign vd = vz; + assign size = sizez; + assign sizelz = req_size; + +endmodule + + +//------------------------------------------------------------------ +//-- OUTPUT ENTITIES +//------------------------------------------------------------------ + +module mgc_out_stdreg (d, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input [width-1:0] d; + output [width-1:0] z; + + wire [width-1:0] z; + + assign z = d; + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_stdreg_en (ld, d, lz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ld; + input [width-1:0] d; + output lz; + output [width-1:0] z; + + wire lz; + wire [width-1:0] z; + + assign z = d; + assign lz = ld; + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_stdreg_wait (ld, vd, d, lz, vz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + + wire vd; + wire lz; + wire [width-1:0] z; + + assign z = d; + assign lz = ld; + assign vd = vz; + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_prereg_en (ld, d, lz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ld; + input [width-1:0] d; + output lz; + output [width-1:0] z; + + wire lz; + wire [width-1:0] z; + + assign z = d; + assign lz = ld; + +endmodule + +//------------------------------------------------------------------ +//-- INOUT ENTITIES +//------------------------------------------------------------------ + +module mgc_inout_stdreg_en (ldin, din, ldout, dout, lzin, lzout, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ldin; + output [width-1:0] din; + input ldout; + input [width-1:0] dout; + output lzin; + output lzout; + inout [width-1:0] z; + + wire [width-1:0] din; + wire lzin; + wire lzout; + wire [width-1:0] z; + + assign lzin = ldin; + assign din = ldin ? z : {width{1'bz}}; + assign lzout = ldout; + assign z = ldout ? dout : {width{1'bz}}; + +endmodule + +//------------------------------------------------------------------ +module hid_tribuf( I_SIG, ENABLE, O_SIG); + parameter integer width = 8; + + input [width-1:0] I_SIG; + input ENABLE; + inout [width-1:0] O_SIG; + + assign O_SIG = (ENABLE) ? I_SIG : { width{1'bz}}; + +endmodule +//------------------------------------------------------------------ + +module mgc_inout_stdreg_wait (ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + input ldin; + output vdin; + output [width-1:0] din; + input ldout; + output vdout; + input [width-1:0] dout; + output lzin; + input vzin; + output lzout; + input vzout; + inout [width-1:0] z; + + wire vdin; + wire [width-1:0] din; + wire vdout; + wire lzin; + wire lzout; + wire [width-1:0] z; + wire ldout_and_vzout; + + assign lzin = ldin; + assign vdin = vzin; + assign din = ldin ? z : {width{1'bz}}; + assign lzout = ldout; + assign vdout = vzout ; + assign ldout_and_vzout = ldout && vzout ; + + hid_tribuf #(width) tb( .I_SIG(dout), + .ENABLE(ldout_and_vzout), + .O_SIG(z) ); + +endmodule + +//------------------------------------------------------------------ + +module mgc_inout_buf_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z); + + parameter integer rscid = 0; // resource ID + parameter integer width = 8; // fifo width + parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge + parameter ph_en = 1'b1; // clock enable polarity + parameter ph_arst = 1'b1; // async reset polarity + parameter ph_srst = 1'b1; // sync reset polarity + + input clk; + input en; + input arst; + input srst; + input ldin; + output vdin; + output [width-1:0] din; + input ldout; + output vdout; + input [width-1:0] dout; + output lzin; + input vzin; + output lzout; + input vzout; + inout [width-1:0] z; + + wire lzout_buf; + wire vzout_buf; + wire [width-1:0] z_buf; + wire vdin; + wire [width-1:0] din; + wire vdout; + wire lzin; + wire lzout; + wire [width-1:0] z; + + assign lzin = ldin; + assign vdin = vzin; + assign din = ldin ? z : {width{1'bz}}; + assign lzout = lzout_buf & ~ldin; + assign vzout_buf = vzout & ~ldin; + hid_tribuf #(width) tb( .I_SIG(z_buf), + .ENABLE((lzout_buf && (!ldin) && vzout) ), + .O_SIG(z) ); + + mgc_out_buf_wait + #( + .rscid (rscid), + .width (width), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + BUFF + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ldout), + .vd (vdout), + .d (dout), + .lz (lzout_buf), + .vz (vzout_buf), + .z (z_buf) + ); + + +endmodule + +module mgc_inout_fifo_wait (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, lzin, vzin, lzout, vzout, z); + + parameter integer rscid = 0; // resource ID + parameter integer width = 8; // fifo width + parameter integer fifo_sz = 8; // fifo depth + parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge + parameter ph_en = 1'b1; // clock enable polarity + parameter ph_arst = 1'b1; // async reset polarity + parameter ph_srst = 1'b1; // sync reset polarity + parameter integer ph_log2 = 3; // log2(fifo_sz) + parameter integer pwropt = 0; // pwropt + + input clk; + input en; + input arst; + input srst; + input ldin; + output vdin; + output [width-1:0] din; + input ldout; + output vdout; + input [width-1:0] dout; + output lzin; + input vzin; + output lzout; + input vzout; + inout [width-1:0] z; + + wire lzout_buf; + wire vzout_buf; + wire [width-1:0] z_buf; + wire comb; + wire vdin; + wire [width-1:0] din; + wire vdout; + wire lzin; + wire lzout; + wire [width-1:0] z; + + assign lzin = ldin; + assign vdin = vzin; + assign din = ldin ? z : {width{1'bz}}; + assign lzout = lzout_buf & ~ldin; + assign vzout_buf = vzout & ~ldin; + assign comb = (lzout_buf && (!ldin) && vzout); + + hid_tribuf #(width) tb2( .I_SIG(z_buf), .ENABLE(comb), .O_SIG(z) ); + + mgc_out_fifo_wait + #( + .rscid (rscid), + .width (width), + .fifo_sz (fifo_sz), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst), + .ph_log2 (ph_log2), + .pwropt (pwropt) + ) + FIFO + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ldout), + .vd (vdout), + .d (dout), + .lz (lzout_buf), + .vz (vzout_buf), + .z (z_buf) + ); + +endmodule + +//------------------------------------------------------------------ +//-- I/O SYNCHRONIZATION ENTITIES +//------------------------------------------------------------------ + +module mgc_io_sync (ld, lz); + + input ld; + output lz; + + assign lz = ld; + +endmodule + +module mgc_bsync_rdy (rd, rz); + + parameter integer rscid = 0; // resource ID + parameter ready = 1; + parameter valid = 0; + + input rd; + output rz; + + wire rz; + + assign rz = rd; + +endmodule + +module mgc_bsync_vld (vd, vz); + + parameter integer rscid = 0; // resource ID + parameter ready = 0; + parameter valid = 1; + + output vd; + input vz; + + wire vd; + + assign vd = vz; + +endmodule + +module mgc_bsync_rv (rd, vd, rz, vz); + + parameter integer rscid = 0; // resource ID + parameter ready = 1; + parameter valid = 1; + + input rd; + output vd; + output rz; + input vz; + + wire vd; + wire rz; + + assign rz = rd; + assign vd = vz; + +endmodule + +//------------------------------------------------------------------ + +module mgc_sync (ldin, vdin, ldout, vdout); + + input ldin; + output vdin; + input ldout; + output vdout; + + wire vdin; + wire vdout; + + assign vdin = ldout; + assign vdout = ldin; + +endmodule + +/////////////////////////////////////////////////////////////////////////////// +// dummy function used to preserve funccalls for modulario +// it looks like a memory read to the caller +/////////////////////////////////////////////////////////////////////////////// +module funccall_inout (d, ad, bd, z, az, bz); + + parameter integer ram_id = 1; + parameter integer width = 8; + parameter integer addr_width = 8; + + output [width-1:0] d; + input [addr_width-1:0] ad; + input bd; + input [width-1:0] z; + output [addr_width-1:0] az; + output bz; + + wire [width-1:0] d; + wire [addr_width-1:0] az; + wire bz; + + assign d = z; + assign az = ad; + assign bz = bd; + +endmodule + + +/////////////////////////////////////////////////////////////////////////////// +// inlinable modular io not otherwise found in mgc_ioport +/////////////////////////////////////////////////////////////////////////////// + +module modulario_en_in (vd, d, vz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + + output vd; + output [width-1:0] d; + input vz; + input [width-1:0] z; + + wire [width-1:0] d; + wire vd; + + assign d = z; + assign vd = vz; + +endmodule + +//------> ./rtl_mgc_ioport_v2001.v +//------------------------------------------------------------------ + +module mgc_out_reg_pos (clk, en, arst, srst, ld, d, lz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + parameter ph_en = 1'b1; + parameter ph_arst = 1'b1; + parameter ph_srst = 1'b1; + + input clk; + input en; + input arst; + input srst; + input ld; + input [width-1:0] d; + output lz; + output [width-1:0] z; + + reg lz; + reg [width-1:0] z; + + generate + if (ph_arst == 1'b0) + begin: NEG_ARST + always @(posedge clk or negedge arst) + if (arst == 1'b0) + begin: B1 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (srst == ph_srst) + begin: B2 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (en == ph_en) + begin: B3 + lz <= ld; + z <= (ld) ? d : z; + end + end + else + begin: POS_ARST + always @(posedge clk or posedge arst) + if (arst == 1'b1) + begin: B1 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (srst == ph_srst) + begin: B2 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (en == ph_en) + begin: B3 + lz <= ld; + z <= (ld) ? d : z; + end + end + endgenerate + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_reg_neg (clk, en, arst, srst, ld, d, lz, z); + + parameter integer rscid = 1; + parameter integer width = 8; + parameter ph_en = 1'b1; + parameter ph_arst = 1'b1; + parameter ph_srst = 1'b1; + + input clk; + input en; + input arst; + input srst; + input ld; + input [width-1:0] d; + output lz; + output [width-1:0] z; + + reg lz; + reg [width-1:0] z; + + generate + if (ph_arst == 1'b0) + begin: NEG_ARST + always @(negedge clk or negedge arst) + if (arst == 1'b0) + begin: B1 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (srst == ph_srst) + begin: B2 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (en == ph_en) + begin: B3 + lz <= ld; + z <= (ld) ? d : z; + end + end + else + begin: POS_ARST + always @(negedge clk or posedge arst) + if (arst == 1'b1) + begin: B1 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (srst == ph_srst) + begin: B2 + lz <= 1'b0; + z <= {width{1'b0}}; + end + else if (en == ph_en) + begin: B3 + lz <= ld; + z <= (ld) ? d : z; + end + end + endgenerate + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_reg (clk, en, arst, srst, ld, d, lz, z); // Not Supported + + parameter integer rscid = 1; + parameter integer width = 8; + parameter ph_clk = 1'b1; + parameter ph_en = 1'b1; + parameter ph_arst = 1'b1; + parameter ph_srst = 1'b1; + + input clk; + input en; + input arst; + input srst; + input ld; + input [width-1:0] d; + output lz; + output [width-1:0] z; + + + generate + if (ph_clk == 1'b0) + begin: NEG_EDGE + + mgc_out_reg_neg + #( + .rscid (rscid), + .width (width), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + mgc_out_reg_neg_inst + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ld), + .d (d), + .lz (lz), + .z (z) + ); + + end + else + begin: POS_EDGE + + mgc_out_reg_pos + #( + .rscid (rscid), + .width (width), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + mgc_out_reg_pos_inst + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ld), + .d (d), + .lz (lz), + .z (z) + ); + + end + endgenerate + +endmodule + + + + +//------------------------------------------------------------------ + +module mgc_out_buf_wait (clk, en, arst, srst, ld, vd, d, vz, lz, z); // Not supported + + parameter integer rscid = 1; + parameter integer width = 8; + parameter ph_clk = 1'b1; + parameter ph_en = 1'b1; + parameter ph_arst = 1'b1; + parameter ph_srst = 1'b1; + + input clk; + input en; + input arst; + input srst; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + + wire filled; + wire filled_next; + wire [width-1:0] abuf; + wire lbuf; + + + assign filled_next = (filled & (~vz)) | (filled & ld) | (ld & (~vz)); + + assign lbuf = ld & ~(filled ^ vz); + + assign vd = vz | ~filled; + + assign lz = ld | filled; + + assign z = (filled) ? abuf : d; + + wire dummy; + wire dummy_bufreg_lz; + + // Output registers: + mgc_out_reg + #( + .rscid (rscid), + .width (1'b1), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + STATREG + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (filled_next), + .d (1'b0), // input d is unused + .lz (filled), + .z (dummy) // output z is unused + ); + + mgc_out_reg + #( + .rscid (rscid), + .width (width), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + BUFREG + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (lbuf), + .d (d), + .lz (dummy_bufreg_lz), + .z (abuf) + ); + +endmodule + +//------------------------------------------------------------------ + +module mgc_out_fifo_wait (clk, en, arst, srst, ld, vd, d, lz, vz, z); + + parameter integer rscid = 0; // resource ID + parameter integer width = 8; // fifo width + parameter integer fifo_sz = 8; // fifo depth + parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge + parameter ph_en = 1'b1; // clock enable polarity + parameter ph_arst = 1'b1; // async reset polarity + parameter ph_srst = 1'b1; // sync reset polarity + parameter integer ph_log2 = 3; // log2(fifo_sz) + parameter integer pwropt = 0; // pwropt + + + input clk; + input en; + input arst; + input srst; + input ld; // load data + output vd; // fifo full active low + input [width-1:0] d; + output lz; // fifo ready to send + input vz; // dest ready for data + output [width-1:0] z; + + wire [31:0] size; + + + // Output registers: + mgc_out_fifo_wait_core#( + .rscid (rscid), + .width (width), + .sz_width (32), + .fifo_sz (fifo_sz), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst), + .ph_log2 (ph_log2), + .pwropt (pwropt) + ) CORE ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ld), + .vd (vd), + .d (d), + .lz (lz), + .vz (vz), + .z (z), + .size (size) + ); + +endmodule + + + +module mgc_out_fifo_wait_core (clk, en, arst, srst, ld, vd, d, lz, vz, z, size); + + parameter integer rscid = 0; // resource ID + parameter integer width = 8; // fifo width + parameter integer sz_width = 8; // size of port for elements in fifo + parameter integer fifo_sz = 8; // fifo depth + parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge + parameter ph_en = 1'b1; // clock enable polarity + parameter ph_arst = 1'b1; // async reset polarity + parameter ph_srst = 1'b1; // sync reset polarity + parameter integer ph_log2 = 3; // log2(fifo_sz) + parameter integer pwropt = 0; // pwropt + + localparam integer fifo_b = width * fifo_sz; + + input clk; + input en; + input arst; + input srst; + input ld; // load data + output vd; // fifo full active low + input [width-1:0] d; + output lz; // fifo ready to send + input vz; // dest ready for data + output [width-1:0] z; + output [sz_width-1:0] size; + + reg [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat_pre; + wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] stat; + reg [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff_pre; + wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] buff; + reg [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] en_l; + reg [(((fifo_sz > 0) ? fifo_sz : 1)-1)/8:0] en_l_s; + + reg [width-1:0] buff_nxt; + + reg stat_nxt; + reg stat_before; + reg stat_after; + reg en_l_var; + + integer i; + genvar eni; + + wire [32:0] size_t; + reg [31:0] count; + reg [31:0] count_t; + reg [32:0] n_elem; +// pragma translate_off + reg [31:0] peak; +// pragma translate_on + + wire [( (fifo_sz > 0) ? fifo_sz : 1)-1:0] dummy_statreg_lz; + wire [( (fifo_b > 0) ? fifo_b : 1)-1:0] dummy_bufreg_lz; + + generate + if ( fifo_sz > 0 ) + begin: FIFO_REG + assign vd = vz | ~stat[0]; + assign lz = ld | stat[fifo_sz-1]; + assign size_t = (count - (vz && stat[fifo_sz-1])) + ld; + assign size = size_t[sz_width-1:0]; + assign z = (stat[fifo_sz-1]) ? buff[fifo_b-1:width*(fifo_sz-1)] : d; + + always @(*) + begin: FIFOPROC + n_elem = 33'b0; + for (i = fifo_sz-1; i >= 0; i = i - 1) + begin + if (i != 0) + stat_before = stat[i-1]; + else + stat_before = 1'b0; + + if (i != (fifo_sz-1)) + stat_after = stat[i+1]; + else + stat_after = 1'b1; + + stat_nxt = stat_after & + (stat_before | (stat[i] & (~vz)) | (stat[i] & ld) | (ld & (~vz))); + + stat_pre[i] = stat_nxt; + en_l_var = 1'b1; + if (!stat_nxt) + begin + buff_nxt = {width{1'b0}}; + en_l_var = 1'b0; + end + else if (vz && stat_before) + buff_nxt[0+:width] = buff[width*(i-1)+:width]; + else if (ld && !((vz && stat_before) || ((!vz) && stat[i]))) + buff_nxt = d; + else + begin + if (pwropt == 0) + buff_nxt[0+:width] = buff[width*i+:width]; + else + buff_nxt = {width{1'b0}}; + en_l_var = 1'b0; + end + + if (ph_en != 0) + en_l[i] = en & en_l_var; + else + en_l[i] = en | ~en_l_var; + + buff_pre[width*i+:width] = buff_nxt[0+:width]; + + if ((stat_after == 1'b1) && (stat[i] == 1'b0)) + n_elem = ($unsigned(fifo_sz) - 1) - i; + end + + if (ph_en != 0) + en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b1; + else + en_l_s[(((fifo_sz > 0) ? fifo_sz : 1)-1)/8] = 1'b0; + + for (i = fifo_sz-1; i >= 7; i = i - 1) + begin + if ((i%'d2) == 0) + begin + if (ph_en != 0) + en_l_s[(i/8)-1] = en & (stat[i]|stat_pre[i-1]); + else + en_l_s[(i/8)-1] = en | ~(stat[i]|stat_pre[i-1]); + end + end + + if ( stat[fifo_sz-1] == 1'b0 ) + count_t = 32'b0; + else if ( stat[0] == 1'b1 ) + count_t = { {(32-ph_log2){1'b0}}, fifo_sz}; + else + count_t = n_elem[31:0]; + count = count_t; +// pragma translate_off + if ( peak < count ) + peak = count; +// pragma translate_on + end + + if (pwropt == 0) + begin: NOCGFIFO + // Output registers: + mgc_out_reg + #( + .rscid (rscid), + .width (fifo_sz), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + STATREG + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (1'b1), + .d (stat_pre), + .lz (dummy_statreg_lz[0]), + .z (stat) + ); + mgc_out_reg + #( + .rscid (rscid), + .width (fifo_b), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + BUFREG + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (1'b1), + .d (buff_pre), + .lz (dummy_bufreg_lz[0]), + .z (buff) + ); + end + else + begin: CGFIFO + // Output registers: + if ( pwropt > 1) + begin: CGSTATFIFO2 + for (eni = fifo_sz-1; eni >= 0; eni = eni - 1) + begin: pwroptGEN1 + mgc_out_reg + #( + .rscid (rscid), + .width (1), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + STATREG + ( + .clk (clk), + .en (en_l_s[eni/8]), + .arst (arst), + .srst (srst), + .ld (1'b1), + .d (stat_pre[eni]), + .lz (dummy_statreg_lz[eni]), + .z (stat[eni]) + ); + end + end + else + begin: CGSTATFIFO + mgc_out_reg + #( + .rscid (rscid), + .width (fifo_sz), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + STATREG + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (1'b1), + .d (stat_pre), + .lz (dummy_statreg_lz[0]), + .z (stat) + ); + end + for (eni = fifo_sz-1; eni >= 0; eni = eni - 1) + begin: pwroptGEN2 + mgc_out_reg + #( + .rscid (rscid), + .width (width), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst) + ) + BUFREG + ( + .clk (clk), + .en (en_l[eni]), + .arst (arst), + .srst (srst), + .ld (1'b1), + .d (buff_pre[width*eni+:width]), + .lz (dummy_bufreg_lz[eni]), + .z (buff[width*eni+:width]) + ); + end + end + end + else + begin: FEED_THRU + assign vd = vz; + assign lz = ld; + assign z = d; + assign size = ld && !vz; + end + endgenerate + +endmodule + +//------------------------------------------------------------------ +//-- PIPE ENTITIES +//------------------------------------------------------------------ +/* + * + * _______________________________________________ + * WRITER | | READER + * | MGC_PIPE | + * | __________________________ | + * --<| vdout --<| vd --------------- vz<|-----ldin<|--- + * | | FIFO | | + * ---|>ldout ---|>ld ---------------- lz |> ---vdin |>-- + * ---|>dout -----|>d ---------------- dz |> ----din |>-- + * | |________________________| | + * |_______________________________________________| + */ +// two clock pipe +module mgc_pipe (clk, en, arst, srst, ldin, vdin, din, ldout, vdout, dout, size, req_size); + + parameter integer rscid = 0; // resource ID + parameter integer width = 8; // fifo width + parameter integer sz_width = 8; // width of size of elements in fifo + parameter integer fifo_sz = 8; // fifo depth + parameter integer log2_sz = 3; // log2(fifo_sz) + parameter ph_clk = 1'b1; // clock polarity 1=rising edge, 0=falling edge + parameter ph_en = 1'b1; // clock enable polarity + parameter ph_arst = 1'b1; // async reset polarity + parameter ph_srst = 1'b1; // sync reset polarity + parameter integer pwropt = 0; // pwropt + + input clk; + input en; + input arst; + input srst; + input ldin; + output vdin; + output [width-1:0] din; + input ldout; + output vdout; + input [width-1:0] dout; + output [sz_width-1:0] size; + input req_size; + + + mgc_out_fifo_wait_core + #( + .rscid (rscid), + .width (width), + .sz_width (sz_width), + .fifo_sz (fifo_sz), + .ph_clk (ph_clk), + .ph_en (ph_en), + .ph_arst (ph_arst), + .ph_srst (ph_srst), + .ph_log2 (log2_sz), + .pwropt (pwropt) + ) + FIFO + ( + .clk (clk), + .en (en), + .arst (arst), + .srst (srst), + .ld (ldout), + .vd (vdout), + .d (dout), + .lz (vdin), + .vz (ldin), + .z (din), + .size (size) + ); + +endmodule + + +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 2011a.126 Production Release +// HLS Date: Wed Aug 8 00:52:07 PDT 2012 +// +// Generated by: mg3115@EEWS104A-015 +// Generated date: Tue Mar 01 15:39:39 2016 +// ---------------------------------------------------------------------- + +// +// ------------------------------------------------------------------ +// Design Unit: dot_product_core +// ------------------------------------------------------------------ + + +module dot_product_core ( + clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d +); + input clk; + input en; + input arst_n; + input [7:0] input_a_rsc_mgc_in_wire_d; + input [7:0] input_b_rsc_mgc_in_wire_d; + output [7:0] output_rsc_mgc_out_stdreg_d; + reg [7:0] output_rsc_mgc_out_stdreg_d; + + + // Interconnect Declarations + reg exit_MAC_lpi; + reg [7:0] acc_sva_1; + reg [2:0] i_1_sva_1; + wire [2:0] MAC_acc_itm; + wire [3:0] nl_MAC_acc_itm; + wire [7:0] acc_sva_2; + wire [8:0] nl_acc_sva_2; + wire [2:0] i_1_sva_2; + wire [3:0] nl_i_1_sva_2; + + + // Interconnect Declarations for Component Instantiations + assign nl_acc_sva_2 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d + * input_b_rsc_mgc_in_wire_d); + assign acc_sva_2 = nl_acc_sva_2[7:0]; + assign nl_i_1_sva_2 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1; + assign i_1_sva_2 = nl_i_1_sva_2[2:0]; + assign nl_MAC_acc_itm = i_1_sva_2 + 3'b11; + assign MAC_acc_itm = nl_MAC_acc_itm[2:0]; + always @(posedge clk or negedge arst_n) begin + if ( ~ arst_n ) begin + output_rsc_mgc_out_stdreg_d <= 8'b0; + acc_sva_1 <= 8'b0; + i_1_sva_1 <= 3'b0; + exit_MAC_lpi <= 1'b1; + end + else begin + if ( en ) begin + output_rsc_mgc_out_stdreg_d <= MUX_v_8_2_2({acc_sva_2 , output_rsc_mgc_out_stdreg_d}, + MAC_acc_itm[2]); + acc_sva_1 <= acc_sva_2; + i_1_sva_1 <= i_1_sva_2; + exit_MAC_lpi <= ~ (MAC_acc_itm[2]); + end + end + end + + function [7:0] signext_8_1; + input [0:0] vector; + begin + signext_8_1= {{7{vector[0]}}, vector}; + end + endfunction + + + function [2:0] signext_3_1; + input [0:0] vector; + begin + signext_3_1= {{2{vector[0]}}, vector}; + end + endfunction + + + function [7:0] MUX_v_8_2_2; + input [15:0] inputs; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = inputs[15:8]; + end + 1'b1 : begin + result = inputs[7:0]; + end + default : begin + result = inputs[15:8]; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + + + function signed [7:0] conv_s2s_16_8 ; + input signed [15:0] vector ; + begin + conv_s2s_16_8 = vector[7:0]; + end + endfunction + +endmodule + +// ------------------------------------------------------------------ +// Design Unit: dot_product +// Generated from file(s): +// 2) $PROJECT_HOME/../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp +// ------------------------------------------------------------------ + + +module dot_product ( + input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n +); + input [7:0] input_a_rsc_z; + input [7:0] input_b_rsc_z; + output [7:0] output_rsc_z; + input clk; + input en; + input arst_n; + + + // Interconnect Declarations + wire [7:0] input_a_rsc_mgc_in_wire_d; + wire [7:0] input_b_rsc_mgc_in_wire_d; + wire [7:0] output_rsc_mgc_out_stdreg_d; + + + // Interconnect Declarations for Component Instantiations + mgc_in_wire #(.rscid(1), + .width(8)) input_a_rsc_mgc_in_wire ( + .d(input_a_rsc_mgc_in_wire_d), + .z(input_a_rsc_z) + ); + mgc_in_wire #(.rscid(2), + .width(8)) input_b_rsc_mgc_in_wire ( + .d(input_b_rsc_mgc_in_wire_d), + .z(input_b_rsc_z) + ); + mgc_out_stdreg #(.rscid(3), + .width(8)) output_rsc_mgc_out_stdreg ( + .d(output_rsc_mgc_out_stdreg_d), + .z(output_rsc_z) + ); + dot_product_core dot_product_core_inst ( + .clk(clk), + .en(en), + .arst_n(arst_n), + .input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d), + .input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d), + .output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d) + ); +endmodule + + + |