diff options
Diffstat (limited to 'dot_product/dot_product/dot_product.v4/directives.tcl')
| -rw-r--r-- | dot_product/dot_product/dot_product.v4/directives.tcl | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/dot_product/dot_product/dot_product.v4/directives.tcl b/dot_product/dot_product/dot_product.v4/directives.tcl new file mode 100644 index 0000000..17e63b7 --- /dev/null +++ b/dot_product/dot_product/dot_product.v4/directives.tcl @@ -0,0 +1,59 @@ +// Catapult University Version 2011a.126 (Production Release) Wed Aug 8 00:52:07 PDT 2012 +// +// Copyright (c) Calypto Design Systems, Inc., 1996-2012, All Rights Reserved. +// UNPUBLISHED, LICENSED SOFTWARE. +// CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE +// PROPERTY OF CALYPTO DESIGN SYSTEMS OR ITS LICENSORS +// +// Running on Windows 7 mg3115@EEWS104A-015 Service Pack 1 6.01.7601 i686 +// +// Package information: SIFLIBS v17.0_1.1, HLS_PKGS v17.0_1.1, +// DesignPad v2.78_0.0 +// +// This version may only be used for academic purposes. Some optimizations +// are disabled, so results obtained from this version may be sub-optimal. +// +project new +flow package require /SCVerify +solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp} -type C++ +solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.h} -type CHEADER +solution file add {../student_files_2015/student_files_2015/prj1/dot_product_source/tb_dot_product.cpp} -type C++ +directive set -REGISTER_IDLE_SIGNAL false +directive set -IDLE_SIGNAL {} +directive set -TRANSACTION_DONE_SIGNAL false +directive set -DONE_FLAG {} +directive set -START_FLAG {} +directive set -FSM_ENCODING none +directive set -REG_MAX_FANOUT 0 +directive set -NO_X_ASSIGNMENTS true +directive set -SAFE_FSM false +directive set -RESET_CLEARS_ALL_REGS true +directive set -ASSIGN_OVERHEAD 0 +directive set -DESIGN_GOAL area +directive set -OLD_SCHED false +directive set -PIPELINE_RAMP_UP true +directive set -COMPGRADE fast +directive set -SPECULATE true +directive set -MERGEABLE true +directive set -REGISTER_THRESHOLD 256 +directive set -MEM_MAP_THRESHOLD 32 +directive set -UNROLL no +directive set -CLOCK_OVERHEAD 20.000000 +directive set -OPT_CONST_MULTS -1 +go analyze +directive set -CLOCK_NAME clk +directive set -CLOCKS {clk {-CLOCK_PERIOD 20.0 -CLOCK_EDGE rising -CLOCK_UNCERTAINTY 0.0 -CLOCK_HIGH_TIME 10.0 -RESET_SYNC_NAME rst -RESET_ASYNC_NAME arst_n -RESET_KIND async -RESET_SYNC_ACTIVE high -RESET_ASYNC_ACTIVE low -ENABLE_NAME en -ENABLE_ACTIVE high}} +directive set -TECHLIBS {{Altera_accel_CycloneIII.lib Altera_accel_CycloneIII} {mgc_Altera-Cyclone-III-6_beh_psr.lib {{mgc_Altera-Cyclone-III-6_beh_psr part EP3C16F484C}}}} +directive set -DESIGN_HIERARCHY dot_product +go compile +directive set /dot_product/core/main -DISTRIBUTED_PIPELINE true +directive set /dot_product/input_b -STREAM 8 +directive set /dot_product/input_b -WORD_WIDTH 8 +directive set /dot_product/core/MAC -DISTRIBUTED_PIPELINE true +directive set /dot_product/core/MAC -PIPELINE_INIT_INTERVAL 1 +directive set /dot_product/input_a -STREAM 8 +directive set /dot_product/input_a -WORD_WIDTH 8 +directive set /dot_product/core/main -PIPELINE_INIT_INTERVAL 0 +directive set /dot_product/core/MAC -UNROLL yes +go architect +go allocate |