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+--a_gray2bin carry_chain="MANUAL" carry_chain_length=48 device_family="Cyclone III" ignore_carry_buffers="OFF" WIDTH=10 bin gray
+--VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2013 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+
+--synthesis_resources =
+SUBDESIGN a_gray2bin_tgb
+(
+ bin[9..0] : output;
+ gray[9..0] : input;
+)
+VARIABLE
+ xor0 : WIRE;
+ xor1 : WIRE;
+ xor2 : WIRE;
+ xor3 : WIRE;
+ xor4 : WIRE;
+ xor5 : WIRE;
+ xor6 : WIRE;
+ xor7 : WIRE;
+ xor8 : WIRE;
+
+BEGIN
+ bin[] = ( gray[9..9], xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0);
+ xor0 = (gray[0..0] $ xor1);
+ xor1 = (gray[1..1] $ xor2);
+ xor2 = (gray[2..2] $ xor3);
+ xor3 = (gray[3..3] $ xor4);
+ xor4 = (gray[4..4] $ xor5);
+ xor5 = (gray[5..5] $ xor6);
+ xor6 = (gray[6..6] $ xor7);
+ xor7 = (gray[7..7] $ xor8);
+ xor8 = (gray[9..9] $ gray[8..8]);
+END;
+--VALID FILE