verilog - Repository with some Verilog designs used to learn Verilog simulation.

Branch	Commit message	Author	Age
master	adding mux	zedarider	8 years


Age	Commit message	Author	Files	Lines
2016-05-09	adding muxHEAD master	zedarider	1	-1/+1
2016-05-09	Merge branch 'master' of https://github.com/zedarider/verilog	zedarider	432	-37/+239923
2016-05-09	adding mux	zedarider	1	-0/+84
2016-05-07	adding Quartus files	unknown	432	-37/+239923
2016-05-07	adding column_chooser	zedarider	1	-0/+77
2016-05-06	adding all files	zedarider	2	-0/+40
2016-05-05	adding project verilog file for row detection	zedarider	2	-0/+43
2016-03-01	Put into Folder	zedarider	2	-0/+0
2016-03-01	adding HelloWorld Demo	zedarider	1	-0/+0
2016-03-01	adding HelloWorld Demo	zedarider	1	-8/+0
[...]

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