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| author | zedarider <ymherklotz@gmail.com> | 2016-05-09 16:25:51 +0200 |
|---|---|---|
| committer | zedarider <ymherklotz@gmail.com> | 2016-05-09 16:25:51 +0200 |
| commit | 04dcd908cc7eb3c9f064f2ecf73cebc0cd4f7f70 (patch) | |
| tree | 5931b503bc3f1340f0ce3407c13ddbad7184bdb7 | |
| parent | 36133c2ec82ea8f58a5301c9127f15e12d052218 (diff) | |
| download | verilog-04dcd908cc7eb3c9f064f2ecf73cebc0cd4f7f70.tar.gz verilog-04dcd908cc7eb3c9f064f2ecf73cebc0cd4f7f70.zip | |
| -rw-r--r-- | special_note_mux.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/special_note_mux.v b/special_note_mux.v index 38932ca..7de1817 100644 --- a/special_note_mux.v +++ b/special_note_mux.v @@ -44,7 +44,7 @@ module special_note_mux(clk_in, x_in0, x_in1, x_in2, x_in3, x_in4, x_in5, x_in6, always @(posedge clk_in) begin - if(counter < 32) + if(counter < 6d'32) begin if(counter == 6d'0) x_out = x_in0; if(counter == 6d'1) x_out = x_in1; |