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| author | Yann Herklotz <ymherklotz@gmail.com> | 2016-03-01 16:57:28 +0000 |
|---|---|---|
| committer | Yann Herklotz <ymherklotz@gmail.com> | 2016-03-01 16:57:28 +0000 |
| commit | e962509eeed79f58f4492eb27d89f56aa23afa52 (patch) | |
| tree | 9c3718b7bd7661975ea50bc52e76052716ec0227 | |
| parent | 8d4fcb973da587d328a81d7b83cd910afbe5c94f (diff) | |
| download | verilog-e962509eeed79f58f4492eb27d89f56aa23afa52.tar.gz verilog-e962509eeed79f58f4492eb27d89f56aa23afa52.zip | |
Update README.md
| -rw-r--r-- | README.md | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -1 +1,3 @@ -# verilog
\ No newline at end of file +# verilog + +Verilog projects that we have been working on to try and learn verilog. |