diff options
Diffstat (limited to 'TestVerilog/db/TestVerilog.map.qmsg')
| -rw-r--r-- | TestVerilog/db/TestVerilog.map.qmsg | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/TestVerilog/db/TestVerilog.map.qmsg b/TestVerilog/db/TestVerilog.map.qmsg new file mode 100644 index 0000000..4111006 --- /dev/null +++ b/TestVerilog/db/TestVerilog.map.qmsg @@ -0,0 +1,78 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1462613818668 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1462613818669 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 07 10:36:58 2016 " "Processing started: Sat May 07 10:36:58 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1462613818669 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1462613818669 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TestVerilog -c TestVerilog " "Command: quartus_map --read_settings_files=on --write_settings_files=off TestVerilog -c TestVerilog" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1462613818669 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1462613819100 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "testverilog.v 1 1 " "Found 1 design units, including 1 entities, in source file testverilog.v" { { "Info" "ISGN_ENTITY_NAME" "1 TestVerilog " "Found entity 1: TestVerilog" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462613819193 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462613819193 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "TestVerilog " "Elaborating entity \"TestVerilog\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1462613819502 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(43) " "Verilog HDL assignment warning at TestVerilog.v(43): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819503 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(44) " "Verilog HDL assignment warning at TestVerilog.v(44): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 44 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819503 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(45) " "Verilog HDL assignment warning at TestVerilog.v(45): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 45 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819503 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(46) " "Verilog HDL assignment warning at TestVerilog.v(46): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 46 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819504 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(47) " "Verilog HDL assignment warning at TestVerilog.v(47): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819504 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(48) " "Verilog HDL assignment warning at TestVerilog.v(48): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 48 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819504 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(49) " "Verilog HDL assignment warning at TestVerilog.v(49): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 49 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819505 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(50) " "Verilog HDL assignment warning at TestVerilog.v(50): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 50 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819505 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(51) " "Verilog HDL assignment warning at TestVerilog.v(51): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 51 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819505 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(52) " "Verilog HDL assignment warning at TestVerilog.v(52): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 52 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819505 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(53) " "Verilog HDL assignment warning at TestVerilog.v(53): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819506 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(54) " "Verilog HDL assignment warning at TestVerilog.v(54): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 54 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819506 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(55) " "Verilog HDL assignment warning at TestVerilog.v(55): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 55 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819506 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(56) " "Verilog HDL assignment warning at TestVerilog.v(56): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 56 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819507 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(57) " "Verilog HDL assignment warning at TestVerilog.v(57): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 57 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819507 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(58) " "Verilog HDL assignment warning at TestVerilog.v(58): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 58 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819507 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(59) " "Verilog HDL assignment warning at TestVerilog.v(59): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 59 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819507 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(60) " "Verilog HDL assignment warning at TestVerilog.v(60): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 60 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819508 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(61) " "Verilog HDL assignment warning at TestVerilog.v(61): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819508 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(62) " "Verilog HDL assignment warning at TestVerilog.v(62): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 62 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819508 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(63) " "Verilog HDL assignment warning at TestVerilog.v(63): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 63 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819509 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(64) " "Verilog HDL assignment warning at TestVerilog.v(64): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 64 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819509 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(65) " "Verilog HDL assignment warning at TestVerilog.v(65): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 65 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819509 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(66) " "Verilog HDL assignment warning at TestVerilog.v(66): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 66 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819509 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(67) " "Verilog HDL assignment warning at TestVerilog.v(67): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 67 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819510 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(68) " "Verilog HDL assignment warning at TestVerilog.v(68): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 68 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819510 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(69) " "Verilog HDL assignment warning at TestVerilog.v(69): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 69 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819510 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(70) " "Verilog HDL assignment warning at TestVerilog.v(70): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 70 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819510 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(71) " "Verilog HDL assignment warning at TestVerilog.v(71): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819511 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(72) " "Verilog HDL assignment warning at TestVerilog.v(72): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 72 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819511 "|TestVerilog"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 TestVerilog.v(73) " "Verilog HDL assignment warning at TestVerilog.v(73): truncated value with size 32 to match size of target (10)" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 73 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462613819511 "|TestVerilog"} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "10 " "Inferred 10 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "TestVerilog.v" "Mult0" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult1\"" { } { { "TestVerilog.v" "Mult1" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 55 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult2\"" { } { { "TestVerilog.v" "Mult2" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult3\"" { } { { "TestVerilog.v" "Mult3" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 63 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult4\"" { } { { "TestVerilog.v" "Mult4" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 64 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult5\"" { } { { "TestVerilog.v" "Mult5" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 65 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult6\"" { } { { "TestVerilog.v" "Mult6" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 67 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult7\"" { } { { "TestVerilog.v" "Mult7" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 68 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult8\"" { } { { "TestVerilog.v" "Mult8" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 69 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult9 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult9\"" { } { { "TestVerilog.v" "Mult9" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 71 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819799 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1462613819799 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819890 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613819890 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613819989 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820034 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\] lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820103 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1eh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_1eh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1eh " "Found entity 1: add_sub_1eh" { } { { "db/add_sub_1eh.tdf" "" { Text "C:/git/verilog/TestVerilog/db/add_sub_1eh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462613820227 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462613820227 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820259 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820265 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_cfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_cfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_cfh " "Found entity 1: add_sub_cfh" { } { { "db/add_sub_cfh.tdf" "" { Text "C:/git/verilog/TestVerilog/db/add_sub_cfh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462613820326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462613820326 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|altshift:external_latency_ffs lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820372 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult1 " "Elaborated megafunction instantiation \"lpm_mult:Mult1\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 55 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult1 " "Instantiated megafunction \"lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820380 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 55 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820380 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult2 " "Instantiated megafunction \"lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820408 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820408 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820412 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820415 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\] lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820421 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_2eh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_2eh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_2eh " "Found entity 1: add_sub_2eh" { } { { "db/add_sub_2eh.tdf" "" { Text "C:/git/verilog/TestVerilog/db/add_sub_2eh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462613820482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462613820482 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820493 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820498 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_dfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_dfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_dfh " "Found entity 1: add_sub_dfh" { } { { "db/add_sub_dfh.tdf" "" { Text "C:/git/verilog/TestVerilog/db/add_sub_dfh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462613820561 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462613820561 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|altshift:external_latency_ffs lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820567 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult3 " "Elaborated megafunction instantiation \"lpm_mult:Mult3\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 63 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult3 " "Instantiated megafunction \"lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820574 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 63 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820574 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult4 " "Elaborated megafunction instantiation \"lpm_mult:Mult4\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 64 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult4 " "Instantiated megafunction \"lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820602 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 64 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820602 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult5 " "Elaborated megafunction instantiation \"lpm_mult:Mult5\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 65 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult5 " "Instantiated megafunction \"lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820631 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 65 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820631 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult6 " "Elaborated megafunction instantiation \"lpm_mult:Mult6\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 67 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult6 " "Instantiated megafunction \"lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820662 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 67 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820662 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult7 " "Elaborated megafunction instantiation \"lpm_mult:Mult7\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 68 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult7 " "Instantiated megafunction \"lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820692 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 68 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820692 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult8 " "Elaborated megafunction instantiation \"lpm_mult:Mult8\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 69 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820723 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult8 " "Instantiated megafunction \"lpm_mult:Mult8\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820724 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 69 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820724 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult9 " "Elaborated megafunction instantiation \"lpm_mult:Mult9\"" { } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 71 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult9 " "Instantiated megafunction \"lpm_mult:Mult9\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462613820756 ""} } { { "TestVerilog.v" "" { Text "C:/git/verilog/TestVerilog/TestVerilog.v" 71 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462613820756 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1462613821370 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1462613821861 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462613821861 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "1087 " "Implemented 1087 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1462613821958 ""} { "Info" "ICUT_CUT_TM_OPINS" "320 " "Implemented 320 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1462613821958 ""} { "Info" "ICUT_CUT_TM_LCELLS" "747 " "Implemented 747 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1462613821958 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1462613821958 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 31 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "477 " "Peak virtual memory: 477 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1462613822008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 07 10:37:02 2016 " "Processing ended: Sat May 07 10:37:02 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1462613822008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1462613822008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1462613822008 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1462613822008 ""} |