aboutsummaryrefslogtreecommitdiffstats
path: root/TestVerilog/simulation/qsim/work/_info
diff options
context:
space:
mode:
Diffstat (limited to 'TestVerilog/simulation/qsim/work/_info')
-rw-r--r--TestVerilog/simulation/qsim/work/_info85
1 files changed, 85 insertions, 0 deletions
diff --git a/TestVerilog/simulation/qsim/work/_info b/TestVerilog/simulation/qsim/work/_info
new file mode 100644
index 0000000..144b626
--- /dev/null
+++ b/TestVerilog/simulation/qsim/work/_info
@@ -0,0 +1,85 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\git\verilog\TestVerilog\simulation\qsim
+vTestVerilog
+Z1 IV;QBadi?[z2bf3d4Y@ZPe1
+Z2 VfjQ:fLbdZM3T;OZEWhE_33
+Z3 dC:\git\verilog\TestVerilog\simulation\qsim
+Z4 w1462614045
+Z5 8TestVerilog.vo
+Z6 FTestVerilog.vo
+L0 31
+Z7 OV;L;10.1d;51
+r1
+31
+Z8 !s90 -work|work|TestVerilog.vo|
+Z9 o-work work -O0
+Z10 n@test@verilog
+!i10b 1
+Z11 !s100 IZng7MGzh@Q7]WV_0S:Uz2
+!s85 0
+Z12 !s108 1462614046.494000
+Z13 !s107 TestVerilog.vo|
+!s101 -O0
+vTestVerilog_vlg_check_tst
+!i10b 1
+!s100 D_N@?J1dRe9KW7L>GJ0dg3
+IlNkW^XddL;aRSWZZ_OSC30
+Z14 Vl3n@?co<ldAIK>]PGV7bz0
+R3
+Z15 w1462614044
+Z16 8TestVerilog.vt
+Z17 FTestVerilog.vt
+L0 59
+R7
+r1
+!s85 0
+31
+Z18 !s108 1462614046.708000
+Z19 !s107 TestVerilog.vt|
+Z20 !s90 -work|work|TestVerilog.vt|
+!s101 -O0
+R9
+Z21 n@test@verilog_vlg_check_tst
+vTestVerilog_vlg_sample_tst
+!i10b 1
+Z22 !s100 GaIU93=GliTn@TD?hdii]1
+Z23 IZ;]zDXXozI]g:3E[bP?K[0
+Z24 VeBCFUIWAL:9<0dkd_<7;S1
+R3
+R15
+R16
+R17
+L0 29
+R7
+r1
+!s85 0
+31
+R18
+R19
+R20
+!s101 -O0
+R9
+Z25 n@test@verilog_vlg_sample_tst
+vTestVerilog_vlg_vec_tst
+!i10b 1
+!s100 Pj?YzBbV^9W[dB;XN5I2P3
+IFbg@=1:ze?Cf?PeiWPI7O1
+Z26 Vi:e6ZnUae4<Z@Bb3;LazV1
+R3
+R15
+R16
+R17
+L0 6143
+R7
+r1
+!s85 0
+31
+R18
+R19
+R20
+!s101 -O0
+R9
+Z27 n@test@verilog_vlg_vec_tst