diff options
Diffstat (limited to 'column_ chooser/db/prev_cmp_column_chooser.qmsg')
| -rw-r--r-- | column_ chooser/db/prev_cmp_column_chooser.qmsg | 188 |
1 files changed, 188 insertions, 0 deletions
diff --git a/column_ chooser/db/prev_cmp_column_chooser.qmsg b/column_ chooser/db/prev_cmp_column_chooser.qmsg new file mode 100644 index 0000000..70ce107 --- /dev/null +++ b/column_ chooser/db/prev_cmp_column_chooser.qmsg @@ -0,0 +1,188 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1462616372803 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1462616372804 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 07 11:19:32 2016 " "Processing started: Sat May 07 11:19:32 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1462616372804 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1462616372804 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off column_chooser -c column_chooser " "Command: quartus_map --read_settings_files=on --write_settings_files=off column_chooser -c column_chooser" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1462616372804 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1462616373220 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "column_chooser.v 1 1 " "Found 1 design units, including 1 entities, in source file column_chooser.v" { { "Info" "ISGN_ENTITY_NAME" "1 column_chooser " "Found entity 1: column_chooser" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462616373281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462616373281 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "column_chooser " "Elaborating entity \"column_chooser\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1462616373310 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(43) " "Verilog HDL assignment warning at column_chooser.v(43): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373311 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(44) " "Verilog HDL assignment warning at column_chooser.v(44): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 44 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373311 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(45) " "Verilog HDL assignment warning at column_chooser.v(45): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 45 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373312 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(46) " "Verilog HDL assignment warning at column_chooser.v(46): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 46 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373312 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(47) " "Verilog HDL assignment warning at column_chooser.v(47): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 47 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373313 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(48) " "Verilog HDL assignment warning at column_chooser.v(48): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 48 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373313 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(49) " "Verilog HDL assignment warning at column_chooser.v(49): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 49 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373313 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(50) " "Verilog HDL assignment warning at column_chooser.v(50): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 50 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373313 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(51) " "Verilog HDL assignment warning at column_chooser.v(51): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 51 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373314 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(52) " "Verilog HDL assignment warning at column_chooser.v(52): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 52 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373314 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(53) " "Verilog HDL assignment warning at column_chooser.v(53): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373314 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(54) " "Verilog HDL assignment warning at column_chooser.v(54): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 54 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373315 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(55) " "Verilog HDL assignment warning at column_chooser.v(55): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 55 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373315 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(56) " "Verilog HDL assignment warning at column_chooser.v(56): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 56 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373315 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(57) " "Verilog HDL assignment warning at column_chooser.v(57): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 57 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373316 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(58) " "Verilog HDL assignment warning at column_chooser.v(58): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 58 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373316 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(59) " "Verilog HDL assignment warning at column_chooser.v(59): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 59 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373316 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(60) " "Verilog HDL assignment warning at column_chooser.v(60): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 60 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373316 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(61) " "Verilog HDL assignment warning at column_chooser.v(61): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373317 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(62) " "Verilog HDL assignment warning at column_chooser.v(62): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 62 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373317 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(63) " "Verilog HDL assignment warning at column_chooser.v(63): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 63 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373317 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(64) " "Verilog HDL assignment warning at column_chooser.v(64): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 64 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373317 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(65) " "Verilog HDL assignment warning at column_chooser.v(65): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 65 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373318 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(66) " "Verilog HDL assignment warning at column_chooser.v(66): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 66 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373318 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(67) " "Verilog HDL assignment warning at column_chooser.v(67): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 67 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373318 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(68) " "Verilog HDL assignment warning at column_chooser.v(68): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 68 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373318 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(69) " "Verilog HDL assignment warning at column_chooser.v(69): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 69 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373319 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(70) " "Verilog HDL assignment warning at column_chooser.v(70): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 70 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373319 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(71) " "Verilog HDL assignment warning at column_chooser.v(71): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 71 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373319 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(72) " "Verilog HDL assignment warning at column_chooser.v(72): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 72 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373320 "|column_chooser"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 column_chooser.v(73) " "Verilog HDL assignment warning at column_chooser.v(73): truncated value with size 32 to match size of target (10)" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 73 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1462616373320 "|column_chooser"} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "10 " "Inferred 10 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" { } { { "column_chooser.v" "Mult0" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult1 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult1\"" { } { { "column_chooser.v" "Mult1" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 55 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult2\"" { } { { "column_chooser.v" "Mult2" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult3\"" { } { { "column_chooser.v" "Mult3" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 63 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult4 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult4\"" { } { { "column_chooser.v" "Mult4" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 64 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult5 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult5\"" { } { { "column_chooser.v" "Mult5" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 65 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult6 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult6\"" { } { { "column_chooser.v" "Mult6" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 67 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult7 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult7\"" { } { { "column_chooser.v" "Mult7" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 68 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult8 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult8\"" { } { { "column_chooser.v" "Mult8" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 69 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult9 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult9\"" { } { { "column_chooser.v" "Mult9" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 71 -1 0 } } } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373618 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 -1 1462616373618 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616373689 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373690 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616373690 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373749 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373780 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\] lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373828 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1eh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_1eh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1eh " "Found entity 1: add_sub_1eh" { } { { "db/add_sub_1eh.tdf" "" { Text "C:/git/verilog/column_ chooser/db/add_sub_1eh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462616373893 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462616373893 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373913 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616373926 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_cfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_cfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_cfh " "Found entity 1: add_sub_cfh" { } { { "db/add_sub_cfh.tdf" "" { Text "C:/git/verilog/column_ chooser/db/add_sub_cfh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462616373992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462616373992 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult0\|altshift:external_latency_ffs lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"lpm_mult:Mult0\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 53 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374024 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult1 " "Elaborated megafunction instantiation \"lpm_mult:Mult1\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 55 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult1 " "Instantiated megafunction \"lpm_mult:Mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374050 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 55 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374050 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult2 " "Instantiated megafunction \"lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374096 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374096 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 307 5 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374114 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "multcore.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/multcore.tdf" 228 7 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374121 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\] lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|lpm_add_sub:adder\[1\]\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374135 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_2eh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_2eh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_2eh " "Found entity 1: add_sub_2eh" { } { { "db/add_sub_2eh.tdf" "" { Text "C:/git/verilog/column_ chooser/db/add_sub_2eh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462616374198 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462616374198 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 138 3 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374217 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\] lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|multcore:mult_core\|mpar_add:padder\|mpar_add:sub_par_add\|lpm_add_sub:adder\[0\]\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "mpar_add.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/mpar_add.tdf" 78 8 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374232 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_dfh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_dfh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_dfh " "Found entity 1: add_sub_dfh" { } { { "db/add_sub_dfh.tdf" "" { Text "C:/git/verilog/column_ chooser/db/add_sub_dfh.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1462616374298 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1462616374298 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_mult:Mult2\|altshift:external_latency_ffs lpm_mult:Mult2 " "Elaborated megafunction instantiation \"lpm_mult:Mult2\|altshift:external_latency_ffs\", which is child of megafunction instantiation \"lpm_mult:Mult2\"" { } { { "lpm_mult.tdf" "" { Text "c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mult.tdf" 350 4 0 } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 61 -1 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374311 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult3 " "Elaborated megafunction instantiation \"lpm_mult:Mult3\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 63 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult3 " "Instantiated megafunction \"lpm_mult:Mult3\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374333 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 63 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374333 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult4 " "Elaborated megafunction instantiation \"lpm_mult:Mult4\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 64 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult4 " "Instantiated megafunction \"lpm_mult:Mult4\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374377 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 64 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374377 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult5 " "Elaborated megafunction instantiation \"lpm_mult:Mult5\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 65 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult5 " "Instantiated megafunction \"lpm_mult:Mult5\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374423 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 65 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374423 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult6 " "Elaborated megafunction instantiation \"lpm_mult:Mult6\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 67 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult6 " "Instantiated megafunction \"lpm_mult:Mult6\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374471 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 67 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374471 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult7 " "Elaborated megafunction instantiation \"lpm_mult:Mult7\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 68 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374516 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult7 " "Instantiated megafunction \"lpm_mult:Mult7\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374517 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 68 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374517 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult8 " "Elaborated megafunction instantiation \"lpm_mult:Mult8\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 69 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult8 " "Instantiated megafunction \"lpm_mult:Mult8\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374589 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 69 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374589 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult9 " "Elaborated megafunction instantiation \"lpm_mult:Mult9\"" { } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 71 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult9 " "Instantiated megafunction \"lpm_mult:Mult9\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 5 " "Parameter \"LPM_WIDTHA\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 15 " "Parameter \"LPM_WIDTHB\" = \"15\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT YES " "Parameter \"INPUT_A_IS_CONSTANT\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1462616374636 ""} } { { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 71 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1462616374636 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Quartus II" 0 -1 1462616375254 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1462616375753 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1462616375753 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "1087 " "Implemented 1087 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1462616375869 ""} { "Info" "ICUT_CUT_TM_OPINS" "320 " "Implemented 320 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1462616375869 ""} { "Info" "ICUT_CUT_TM_LCELLS" "747 " "Implemented 747 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1462616375869 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1462616375869 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 31 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 31 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "497 " "Peak virtual memory: 497 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1462616375895 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 07 11:19:35 2016 " "Processing ended: Sat May 07 11:19:35 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1462616375895 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1462616375895 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1462616375895 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1462616375895 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1462616377513 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1462616377513 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 07 11:19:36 2016 " "Processing started: Sat May 07 11:19:36 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1462616377513 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1462616377513 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off column_chooser -c column_chooser " "Command: quartus_fit --read_settings_files=off --write_settings_files=off column_chooser -c column_chooser" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1462616377514 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1462616377636 ""} +{ "Info" "0" "" "Project = column_chooser" { } { } 0 0 "Project = column_chooser" 0 0 "Fitter" 0 0 1462616377637 ""} +{ "Info" "0" "" "Revision = column_chooser" { } { } 0 0 "Revision = column_chooser" 0 0 "Fitter" 0 0 1462616377637 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1462616377701 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "column_chooser EP3C16F484C6 " "Selected device EP3C16F484C6 for design \"column_chooser\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1462616377941 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1462616378000 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1462616378001 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1462616378001 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1462616378088 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C40F484C6 " "Device EP3C40F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1462616378380 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C55F484C6 " "Device EP3C55F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1462616378380 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP3C80F484C6 " "Device EP3C80F484C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1462616378380 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1462616378380 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ D1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 2380 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1462616378384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 2382 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1462616378384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ K2 " "Pin ~ALTERA_DCLK~ is reserved at location K2" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 2384 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1462616378384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ K1 " "Pin ~ALTERA_DATA0~ is reserved at location K1" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 2386 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1462616378384 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ K22 " "Pin ~ALTERA_nCEO~ is reserved at location K22" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 2388 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1462616378384 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1462616378384 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1462616378386 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "340 340 " "No exact pin location assignment(s) for 340 pins of 340 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[0\] " "Pin top_grid_x0\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[1\] " "Pin top_grid_x0\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 58 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[2\] " "Pin top_grid_x0\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[3\] " "Pin top_grid_x0\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 60 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[4\] " "Pin top_grid_x0\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 61 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[5\] " "Pin top_grid_x0\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[6\] " "Pin top_grid_x0\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 63 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[7\] " "Pin top_grid_x0\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 64 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[8\] " "Pin top_grid_x0\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 65 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x0\[9\] " "Pin top_grid_x0\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x0[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 9 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 66 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[0\] " "Pin top_grid_x1\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 67 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[1\] " "Pin top_grid_x1\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 68 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[2\] " "Pin top_grid_x1\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 69 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[3\] " "Pin top_grid_x1\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 70 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[4\] " "Pin top_grid_x1\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 71 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[5\] " "Pin top_grid_x1\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 72 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[6\] " "Pin top_grid_x1\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 73 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[7\] " "Pin top_grid_x1\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 74 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[8\] " "Pin top_grid_x1\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 75 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x1\[9\] " "Pin top_grid_x1\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x1[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 10 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 76 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[0\] " "Pin top_grid_x2\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 77 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[1\] " "Pin top_grid_x2\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 78 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[2\] " "Pin top_grid_x2\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 79 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[3\] " "Pin top_grid_x2\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 80 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[4\] " "Pin top_grid_x2\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 81 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[5\] " "Pin top_grid_x2\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 82 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[6\] " "Pin top_grid_x2\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 83 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[7\] " "Pin top_grid_x2\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 84 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[8\] " "Pin top_grid_x2\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 85 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x2\[9\] " "Pin top_grid_x2\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x2[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 11 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x2[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 86 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[0\] " "Pin top_grid_x3\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 87 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[1\] " "Pin top_grid_x3\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 88 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[2\] " "Pin top_grid_x3\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 89 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[3\] " "Pin top_grid_x3\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 90 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[4\] " "Pin top_grid_x3\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 91 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[5\] " "Pin top_grid_x3\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 92 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[6\] " "Pin top_grid_x3\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 93 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[7\] " "Pin top_grid_x3\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 94 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[8\] " "Pin top_grid_x3\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 95 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x3\[9\] " "Pin top_grid_x3\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x3[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 12 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x3[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 96 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[0\] " "Pin top_grid_x4\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 97 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[1\] " "Pin top_grid_x4\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 98 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[2\] " "Pin top_grid_x4\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 99 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[3\] " "Pin top_grid_x4\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 100 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[4\] " "Pin top_grid_x4\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 101 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[5\] " "Pin top_grid_x4\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 102 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[6\] " "Pin top_grid_x4\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 103 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[7\] " "Pin top_grid_x4\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 104 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[8\] " "Pin top_grid_x4\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 105 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x4\[9\] " "Pin top_grid_x4\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x4[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 13 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x4[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 106 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[0\] " "Pin top_grid_x5\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 107 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[1\] " "Pin top_grid_x5\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 108 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[2\] " "Pin top_grid_x5\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 109 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[3\] " "Pin top_grid_x5\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 110 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[4\] " "Pin top_grid_x5\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 111 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[5\] " "Pin top_grid_x5\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 112 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[6\] " "Pin top_grid_x5\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 113 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[7\] " "Pin top_grid_x5\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 114 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[8\] " "Pin top_grid_x5\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 115 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x5\[9\] " "Pin top_grid_x5\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x5[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 14 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x5[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 116 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[0\] " "Pin top_grid_x6\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 117 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[1\] " "Pin top_grid_x6\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 118 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[2\] " "Pin top_grid_x6\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 119 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[3\] " "Pin top_grid_x6\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 120 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[4\] " "Pin top_grid_x6\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 121 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[5\] " "Pin top_grid_x6\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 122 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[6\] " "Pin top_grid_x6\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 123 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[7\] " "Pin top_grid_x6\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 124 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[8\] " "Pin top_grid_x6\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 125 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x6\[9\] " "Pin top_grid_x6\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x6[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 15 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x6[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 126 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[0\] " "Pin top_grid_x7\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 127 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[1\] " "Pin top_grid_x7\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 128 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[2\] " "Pin top_grid_x7\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 129 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[3\] " "Pin top_grid_x7\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 130 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[4\] " "Pin top_grid_x7\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 131 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[5\] " "Pin top_grid_x7\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 132 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[6\] " "Pin top_grid_x7\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 133 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[7\] " "Pin top_grid_x7\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 134 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[8\] " "Pin top_grid_x7\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 135 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x7\[9\] " "Pin top_grid_x7\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x7[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 16 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x7[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 136 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[0\] " "Pin top_grid_x8\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 137 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[1\] " "Pin top_grid_x8\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 138 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[2\] " "Pin top_grid_x8\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 139 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[3\] " "Pin top_grid_x8\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 140 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[4\] " "Pin top_grid_x8\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 141 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[5\] " "Pin top_grid_x8\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 142 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[6\] " "Pin top_grid_x8\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 143 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[7\] " "Pin top_grid_x8\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 144 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[8\] " "Pin top_grid_x8\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 145 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x8\[9\] " "Pin top_grid_x8\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x8[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 17 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x8[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 146 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[0\] " "Pin top_grid_x9\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 147 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[1\] " "Pin top_grid_x9\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 148 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[2\] " "Pin top_grid_x9\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 149 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[3\] " "Pin top_grid_x9\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 150 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[4\] " "Pin top_grid_x9\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 151 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[5\] " "Pin top_grid_x9\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 152 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[6\] " "Pin top_grid_x9\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 153 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[7\] " "Pin top_grid_x9\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[8\] " "Pin top_grid_x9\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x9\[9\] " "Pin top_grid_x9\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x9[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 18 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x9[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[0\] " "Pin top_grid_x10\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 157 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[1\] " "Pin top_grid_x10\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 158 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[2\] " "Pin top_grid_x10\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 159 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[3\] " "Pin top_grid_x10\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 160 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[4\] " "Pin top_grid_x10\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 161 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[5\] " "Pin top_grid_x10\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 162 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[6\] " "Pin top_grid_x10\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 163 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[7\] " "Pin top_grid_x10\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 164 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[8\] " "Pin top_grid_x10\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 165 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x10\[9\] " "Pin top_grid_x10\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x10[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 19 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x10[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 166 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[0\] " "Pin top_grid_x11\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 167 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[1\] " "Pin top_grid_x11\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 168 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[2\] " "Pin top_grid_x11\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 169 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[3\] " "Pin top_grid_x11\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 170 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[4\] " "Pin top_grid_x11\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 171 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[5\] " "Pin top_grid_x11\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 172 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[6\] " "Pin top_grid_x11\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 173 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[7\] " "Pin top_grid_x11\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 174 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[8\] " "Pin top_grid_x11\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 175 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x11\[9\] " "Pin top_grid_x11\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x11[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 20 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x11[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 176 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[0\] " "Pin top_grid_x12\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 177 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[1\] " "Pin top_grid_x12\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 178 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[2\] " "Pin top_grid_x12\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 179 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[3\] " "Pin top_grid_x12\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 180 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[4\] " "Pin top_grid_x12\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 181 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[5\] " "Pin top_grid_x12\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 182 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[6\] " "Pin top_grid_x12\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 183 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[7\] " "Pin top_grid_x12\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 184 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[8\] " "Pin top_grid_x12\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 185 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x12\[9\] " "Pin top_grid_x12\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x12[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 21 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x12[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 186 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[0\] " "Pin top_grid_x13\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 187 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[1\] " "Pin top_grid_x13\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 188 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[2\] " "Pin top_grid_x13\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 189 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[3\] " "Pin top_grid_x13\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 190 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[4\] " "Pin top_grid_x13\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 191 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[5\] " "Pin top_grid_x13\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 192 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[6\] " "Pin top_grid_x13\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 193 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[7\] " "Pin top_grid_x13\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 194 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[8\] " "Pin top_grid_x13\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 195 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x13\[9\] " "Pin top_grid_x13\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x13[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 22 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x13[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 196 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[0\] " "Pin top_grid_x14\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 197 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[1\] " "Pin top_grid_x14\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 198 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[2\] " "Pin top_grid_x14\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 199 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[3\] " "Pin top_grid_x14\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 200 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[4\] " "Pin top_grid_x14\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 201 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[5\] " "Pin top_grid_x14\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 202 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[6\] " "Pin top_grid_x14\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 203 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[7\] " "Pin top_grid_x14\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 204 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[8\] " "Pin top_grid_x14\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 205 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x14\[9\] " "Pin top_grid_x14\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x14[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 23 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x14[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 206 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[0\] " "Pin top_grid_x15\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 207 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[1\] " "Pin top_grid_x15\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 208 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[2\] " "Pin top_grid_x15\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 209 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[3\] " "Pin top_grid_x15\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 210 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[4\] " "Pin top_grid_x15\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 211 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[5\] " "Pin top_grid_x15\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 212 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[6\] " "Pin top_grid_x15\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 213 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[7\] " "Pin top_grid_x15\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 214 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[8\] " "Pin top_grid_x15\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 215 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x15\[9\] " "Pin top_grid_x15\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x15[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 24 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x15[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 216 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[0\] " "Pin top_grid_x16\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 217 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[1\] " "Pin top_grid_x16\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 218 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[2\] " "Pin top_grid_x16\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 219 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[3\] " "Pin top_grid_x16\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 220 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[4\] " "Pin top_grid_x16\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 221 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[5\] " "Pin top_grid_x16\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 222 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[6\] " "Pin top_grid_x16\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 223 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[7\] " "Pin top_grid_x16\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 224 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[8\] " "Pin top_grid_x16\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 225 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x16\[9\] " "Pin top_grid_x16\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x16[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 25 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x16[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 226 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[0\] " "Pin top_grid_x17\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 227 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[1\] " "Pin top_grid_x17\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 228 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[2\] " "Pin top_grid_x17\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 229 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[3\] " "Pin top_grid_x17\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 230 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[4\] " "Pin top_grid_x17\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 231 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[5\] " "Pin top_grid_x17\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 232 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[6\] " "Pin top_grid_x17\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 233 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[7\] " "Pin top_grid_x17\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 234 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[8\] " "Pin top_grid_x17\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 235 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x17\[9\] " "Pin top_grid_x17\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x17[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 26 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x17[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 236 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[0\] " "Pin top_grid_x18\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 237 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[1\] " "Pin top_grid_x18\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 238 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[2\] " "Pin top_grid_x18\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 239 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[3\] " "Pin top_grid_x18\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 240 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[4\] " "Pin top_grid_x18\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 241 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[5\] " "Pin top_grid_x18\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 242 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[6\] " "Pin top_grid_x18\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 243 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[7\] " "Pin top_grid_x18\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 244 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[8\] " "Pin top_grid_x18\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 245 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x18\[9\] " "Pin top_grid_x18\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x18[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 27 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x18[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 246 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[0\] " "Pin top_grid_x19\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 247 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[1\] " "Pin top_grid_x19\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 248 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[2\] " "Pin top_grid_x19\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 249 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[3\] " "Pin top_grid_x19\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 250 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[4\] " "Pin top_grid_x19\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 251 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[5\] " "Pin top_grid_x19\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 252 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[6\] " "Pin top_grid_x19\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 253 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[7\] " "Pin top_grid_x19\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 254 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[8\] " "Pin top_grid_x19\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 255 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x19\[9\] " "Pin top_grid_x19\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x19[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 28 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x19[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 256 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[0\] " "Pin top_grid_x20\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 257 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[1\] " "Pin top_grid_x20\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 258 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[2\] " "Pin top_grid_x20\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 259 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[3\] " "Pin top_grid_x20\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 260 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[4\] " "Pin top_grid_x20\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 261 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[5\] " "Pin top_grid_x20\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 262 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[6\] " "Pin top_grid_x20\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 263 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[7\] " "Pin top_grid_x20\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 264 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[8\] " "Pin top_grid_x20\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 265 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x20\[9\] " "Pin top_grid_x20\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x20[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 29 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x20[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 266 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[0\] " "Pin top_grid_x21\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 267 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[1\] " "Pin top_grid_x21\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 268 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[2\] " "Pin top_grid_x21\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 269 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[3\] " "Pin top_grid_x21\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 270 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[4\] " "Pin top_grid_x21\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 271 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[5\] " "Pin top_grid_x21\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 272 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[6\] " "Pin top_grid_x21\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 273 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[7\] " "Pin top_grid_x21\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 274 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[8\] " "Pin top_grid_x21\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 275 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x21\[9\] " "Pin top_grid_x21\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x21[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 30 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x21[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 276 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[0\] " "Pin top_grid_x22\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 277 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[1\] " "Pin top_grid_x22\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 278 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[2\] " "Pin top_grid_x22\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 279 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[3\] " "Pin top_grid_x22\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 280 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[4\] " "Pin top_grid_x22\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 281 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[5\] " "Pin top_grid_x22\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 282 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[6\] " "Pin top_grid_x22\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 283 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[7\] " "Pin top_grid_x22\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 284 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[8\] " "Pin top_grid_x22\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 285 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x22\[9\] " "Pin top_grid_x22\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x22[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 31 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x22[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 286 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[0\] " "Pin top_grid_x23\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 287 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[1\] " "Pin top_grid_x23\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 288 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[2\] " "Pin top_grid_x23\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 289 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[3\] " "Pin top_grid_x23\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 290 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[4\] " "Pin top_grid_x23\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 291 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[5\] " "Pin top_grid_x23\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 292 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[6\] " "Pin top_grid_x23\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 293 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[7\] " "Pin top_grid_x23\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 294 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[8\] " "Pin top_grid_x23\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 295 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x23\[9\] " "Pin top_grid_x23\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x23[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 32 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x23[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 296 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[0\] " "Pin top_grid_x24\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 297 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[1\] " "Pin top_grid_x24\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 298 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[2\] " "Pin top_grid_x24\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 299 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[3\] " "Pin top_grid_x24\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 300 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[4\] " "Pin top_grid_x24\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 301 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[5\] " "Pin top_grid_x24\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 302 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[6\] " "Pin top_grid_x24\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 303 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[7\] " "Pin top_grid_x24\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 304 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[8\] " "Pin top_grid_x24\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 305 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x24\[9\] " "Pin top_grid_x24\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x24[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 33 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x24[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 306 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[0\] " "Pin top_grid_x25\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 307 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[1\] " "Pin top_grid_x25\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 308 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[2\] " "Pin top_grid_x25\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 309 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[3\] " "Pin top_grid_x25\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 310 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[4\] " "Pin top_grid_x25\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 311 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[5\] " "Pin top_grid_x25\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 312 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[6\] " "Pin top_grid_x25\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 313 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[7\] " "Pin top_grid_x25\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 314 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[8\] " "Pin top_grid_x25\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 315 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x25\[9\] " "Pin top_grid_x25\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x25[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 34 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x25[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 316 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[0\] " "Pin top_grid_x26\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 317 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[1\] " "Pin top_grid_x26\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 318 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[2\] " "Pin top_grid_x26\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 319 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[3\] " "Pin top_grid_x26\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 320 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[4\] " "Pin top_grid_x26\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 321 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[5\] " "Pin top_grid_x26\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 322 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[6\] " "Pin top_grid_x26\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 323 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[7\] " "Pin top_grid_x26\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 324 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[8\] " "Pin top_grid_x26\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 325 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x26\[9\] " "Pin top_grid_x26\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x26[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 35 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x26[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 326 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[0\] " "Pin top_grid_x27\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 327 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[1\] " "Pin top_grid_x27\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 328 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[2\] " "Pin top_grid_x27\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 329 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[3\] " "Pin top_grid_x27\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 330 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[4\] " "Pin top_grid_x27\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 331 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[5\] " "Pin top_grid_x27\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 332 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[6\] " "Pin top_grid_x27\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 333 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[7\] " "Pin top_grid_x27\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 334 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[8\] " "Pin top_grid_x27\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 335 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x27\[9\] " "Pin top_grid_x27\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x27[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 36 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x27[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 336 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[0\] " "Pin top_grid_x28\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 337 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[1\] " "Pin top_grid_x28\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 338 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[2\] " "Pin top_grid_x28\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 339 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[3\] " "Pin top_grid_x28\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 340 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[4\] " "Pin top_grid_x28\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 341 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[5\] " "Pin top_grid_x28\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 342 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[6\] " "Pin top_grid_x28\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 343 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[7\] " "Pin top_grid_x28\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 344 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[8\] " "Pin top_grid_x28\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 345 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x28\[9\] " "Pin top_grid_x28\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x28[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 37 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x28[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 346 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[0\] " "Pin top_grid_x29\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 347 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[1\] " "Pin top_grid_x29\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 348 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[2\] " "Pin top_grid_x29\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 349 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[3\] " "Pin top_grid_x29\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 350 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[4\] " "Pin top_grid_x29\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 351 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[5\] " "Pin top_grid_x29\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 352 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[6\] " "Pin top_grid_x29\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 353 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[7\] " "Pin top_grid_x29\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 354 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[8\] " "Pin top_grid_x29\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 355 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x29\[9\] " "Pin top_grid_x29\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x29[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 38 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x29[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 356 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[0\] " "Pin top_grid_x30\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 357 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[1\] " "Pin top_grid_x30\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 358 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[2\] " "Pin top_grid_x30\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 359 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[3\] " "Pin top_grid_x30\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 360 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[4\] " "Pin top_grid_x30\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 361 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[5\] " "Pin top_grid_x30\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 362 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[6\] " "Pin top_grid_x30\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 363 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[7\] " "Pin top_grid_x30\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 364 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[8\] " "Pin top_grid_x30\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 365 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x30\[9\] " "Pin top_grid_x30\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x30[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 39 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x30[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 366 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[0\] " "Pin top_grid_x31\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 367 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[1\] " "Pin top_grid_x31\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 368 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[2\] " "Pin top_grid_x31\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 369 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[3\] " "Pin top_grid_x31\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 370 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[4\] " "Pin top_grid_x31\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 371 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[5\] " "Pin top_grid_x31\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 372 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[6\] " "Pin top_grid_x31\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 373 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[7\] " "Pin top_grid_x31\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 374 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[8\] " "Pin top_grid_x31\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 375 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "top_grid_x31\[9\] " "Pin top_grid_x31\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { top_grid_x31[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 40 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { top_grid_x31[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 376 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[0\] " "Pin first_red_pos_x\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[1\] " "Pin first_red_pos_x\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[2\] " "Pin first_red_pos_x\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[3\] " "Pin first_red_pos_x\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 40 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[4\] " "Pin first_red_pos_x\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 41 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[5\] " "Pin first_red_pos_x\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 42 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[6\] " "Pin first_red_pos_x\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 43 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[7\] " "Pin first_red_pos_x\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 44 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[8\] " "Pin first_red_pos_x\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 45 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "first_red_pos_x\[9\] " "Pin first_red_pos_x\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { first_red_pos_x[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 6 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { first_red_pos_x[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 46 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[5\] " "Pin sec_red_pos_x\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[5] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 52 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[4\] " "Pin sec_red_pos_x\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[4] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[3\] " "Pin sec_red_pos_x\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[3] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 50 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[2\] " "Pin sec_red_pos_x\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[2] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[1\] " "Pin sec_red_pos_x\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[1] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 48 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[0\] " "Pin sec_red_pos_x\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[0] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 47 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[6\] " "Pin sec_red_pos_x\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[6] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[7\] " "Pin sec_red_pos_x\[7\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[7] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[8\] " "Pin sec_red_pos_x\[8\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[8] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sec_red_pos_x\[9\] " "Pin sec_red_pos_x\[9\] not assigned to an exact location on the device" { } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { sec_red_pos_x[9] } } } { "column_chooser.v" "" { Text "C:/git/verilog/column_ chooser/column_chooser.v" 7 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sec_red_pos_x[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1462616379250 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1462616379250 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "column_chooser.sdc " "Synopsys Design Constraints File file not found: 'column_chooser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1462616379943 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1462616379943 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1462616379944 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1462616379945 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1462616379949 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1462616379949 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1462616379950 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1462616379956 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1462616379956 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1462616379957 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1462616379958 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1462616379959 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1462616379960 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1462616379960 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1462616379961 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1462616379961 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1462616379962 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1462616379962 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "340 unused 2.5V 20 320 0 " "Number of I/O pins in group: 340 (unused VREF, 2.5V VCCIO, 20 input, 320 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1462616379970 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1462616379970 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1462616379970 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 29 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 29 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 46 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 41 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 41 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 46 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 46 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 42 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 47 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 47 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1462616379971 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1462616379971 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1462616379971 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1462616380292 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1462616381324 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1462616381465 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1462616381477 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1462616383710 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1462616383710 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1462616384489 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X21_Y10 X30_Y19 " "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19" { } { { "loc" "" { Generic "C:/git/verilog/column_ chooser/" { { 1 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} { { 11 { 0 "Router estimated peak interconnect usage is 4% of the available device resources in the region that extends from location X21_Y10 to location X30_Y19"} 21 10 10 10 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1462616385329 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1462616385329 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1462616385430 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1462616385432 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Quartus II" 0 -1 1462616385432 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1462616385432 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.31 " "Total time spent on timing analysis during the Fitter is 0.31 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1462616385451 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1462616385487 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1462616386035 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1462616386064 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1462616386636 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1462616387432 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/git/verilog/column_ chooser/output_files/column_chooser.fit.smsg " "Generated suppressed messages file C:/git/verilog/column_ chooser/output_files/column_chooser.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1462616388638 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1084 " "Peak virtual memory: 1084 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1462616389069 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 07 11:19:49 2016 " "Processing ended: Sat May 07 11:19:49 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1462616389069 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1462616389069 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1462616389069 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1462616389069 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1462616390362 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1462616390363 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 07 11:19:49 2016 " "Processing started: Sat May 07 11:19:49 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1462616390363 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1462616390363 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off column_chooser -c column_chooser " "Command: quartus_asm --read_settings_files=off --write_settings_files=off column_chooser -c column_chooser" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1462616390363 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1462616391261 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1462616391286 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "423 " "Peak virtual memory: 423 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1462616391663 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 07 11:19:51 2016 " "Processing ended: Sat May 07 11:19:51 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1462616391663 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1462616391663 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1462616391663 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1462616391663 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1462616392415 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1462616393370 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1462616393371 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 07 11:19:52 2016 " "Processing started: Sat May 07 11:19:52 2016" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1462616393371 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1462616393371 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta column_chooser -c column_chooser " "Command: quartus_sta column_chooser -c column_chooser" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1462616393371 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1462616393530 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1462616393739 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1462616393739 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1462616393791 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1462616393791 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "column_chooser.sdc " "Synopsys Design Constraints File file not found: 'column_chooser.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1462616394170 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1462616394171 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1462616394171 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1462616394173 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Quartus II" 0 -1 1462616394174 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1462616394174 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1462616394176 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Quartus II" 0 -1 1462616394188 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1462616394189 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394191 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394197 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394199 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394200 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394202 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616394203 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1462616394641 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1462616394675 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1462616395477 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1462616395540 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1462616395541 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1462616395542 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1462616395543 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395544 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395590 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395614 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395637 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395660 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616395682 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1462616396138 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1462616396420 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Quartus II" 0 -1 1462616396420 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Quartus II" 0 -1 1462616396421 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Quartus II" 0 -1 1462616396422 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616396468 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616396514 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616396563 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616396608 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1462616396652 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1462616398423 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1462616398435 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 4 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "501 " "Peak virtual memory: 501 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1462616399171 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 07 11:19:59 2016 " "Processing ended: Sat May 07 11:19:59 2016" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1462616399171 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1462616399171 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1462616399171 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1462616399171 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 39 s " "Quartus II Full Compilation was successful. 0 errors, 39 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1462616400367 ""} |