index
:
verilog
master
Repository with some Verilog designs used to learn Verilog simulation.
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
TestVerilog
/
db
/
TestVerilog.smart_action.txt
blob: 11b531f9db40cbf2cf86311d2d35dbe8cf4f5ca0 (
plain
)
1
SOURCE
