TestVerilog/output_files/TestVerilog.jdi


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<sld_project_info>
  <project>
    <hash md5_digest_80b="785868bd40491843af82"/>
  </project>
  <file_info>
    <file device="EP3C16F484C6" path="TestVerilog.sof" usercode="0xFFFFFFFF"/>
  </file_info>
</sld_project_info>