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author | Clifford Wolf <clifford@clifford.at> | 2019-09-22 13:59:43 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-09-22 13:59:43 +0200 |
commit | 3f9b5048bc26e3fa1cf7d13504f502d28ee99051 (patch) | |
tree | 854e05602de5de7d2c2228bc355e26e6742eb1e5 | |
parent | 881f928e05dca9f1e750ff68793e5cc7653d7ccd (diff) | |
download | picorv32-3f9b5048bc26e3fa1cf7d13504f502d28ee99051.tar.gz picorv32-3f9b5048bc26e3fa1cf7d13504f502d28ee99051.zip |
Fix initialization of "irq" in verilog testbench
Signed-off-by: Clifford Wolf <clifford@clifford.at>
-rw-r--r-- | testbench.v | 2 | ||||
-rw-r--r-- | testbench_wb.v | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/testbench.v b/testbench.v index eee2676..9d8e249 100644 --- a/testbench.v +++ b/testbench.v @@ -75,7 +75,7 @@ module picorv32_wrapper #( output [35:0] trace_data ); wire tests_passed; - reg [31:0] irq; + reg [31:0] irq = 0; reg [15:0] count_cycle = 0; always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0; diff --git a/testbench_wb.v b/testbench_wb.v index e78dbfa..4e1a8eb 100644 --- a/testbench_wb.v +++ b/testbench_wb.v @@ -65,7 +65,7 @@ module picorv32_wrapper #( output [35:0] trace_data ); wire tests_passed; - reg [31:0] irq; + reg [31:0] irq = 0; wire mem_instr; reg [15:0] count_cycle = 0; |