Split out verilator-incompatible code to top-level testbench

Verilator doesn't handle verilog code that deals with time, such
as delayed signals or the repeat task. Clock and reset generation
are therefore moved to a separate file that can be replaced by
a verilator module. VCD generation is also affected by this.

1 files changed, 4 insertions, 4 deletions

diff --git a/Makefile b/Makefile
index f02bda7..9daad19 100644
--- a/Makefile
+++ b/Makefile
@@ -33,12 +33,12 @@ test_axi: testbench.exe firmware/firmware.hex
 test_synth: testbench_synth.exe firmware/firmware.hex
 	vvp -N testbench_synth.exe
 
-testbench.exe: testbench.v axi4_memory.v picorv32.v
-	iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v axi4_memory.v picorv32.v
+testbench.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
+	iverilog -o testbench.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
 	chmod -x testbench.exe
 
-testbench_sp.exe: testbench.v axi4_memory.v picorv32.v
-	iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v axi4_memory.v picorv32.v
+testbench_sp.exe: testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
+	iverilog -o testbench_sp.exe $(subst $(COMPRESSED_ISA),C,-DCOMPRESSED_ISA) -DSP_TEST testbench.v picorv32_wrapper.v axi4_memory.v picorv32.v
 	chmod -x testbench_sp.exe
 
 testbench_synth.exe: testbench.v synth.v