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author | Clifford Wolf <clifford@clifford.at> | 2016-04-12 18:23:32 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-04-12 18:23:32 +0200 |
commit | 4792ef3945245b29faaad734e8b3a4b3f3a82f14 (patch) | |
tree | 8f3709e9655c975f5319362da189f5e9fb55aff7 /README.md | |
parent | 24da68e38ba07e608e334cd1a6ee3b84c457b4d4 (diff) | |
download | picorv32-4792ef3945245b29faaad734e8b3a4b3f3a82f14.tar.gz picorv32-4792ef3945245b29faaad734e8b3a4b3f3a82f14.zip |
Added "picorv32_pcpi_div" module to README.md
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -91,6 +91,7 @@ This Verilog file contains the following Verilog modules: | `picorv32_axi` | The version of the CPU with AXI4-Lite interface | | `picorv32_axi_adapter` | Adapter from PicoRV32 Memory Interface to AXI4-Lite | | `picorv32_pcpi_mul` | A PCPI core that implements the `MUL[H[SU|U]]` instructions | +| `picorv32_pcpi_div` | A PCPI core that implements the `DIV[U]/REM[U]` instructions | Simply copy this file into your project. |