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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
| commit | f4bb91b060211884fc0b85479fb6becf20daeb1f (patch) | |
| tree | d971e626fe57262b7830211644f043477b33c562 /README.md | |
| parent | 490a7345191f9841fa953d18b27c8485171406ce (diff) | |
| download | picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.tar.gz picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.zip | |
RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 16 |
1 files changed, 8 insertions, 8 deletions
@@ -215,9 +215,9 @@ accesses. Set this to 0 to disable the circuitry for catching illegal instructions. -The core will still trap on an `SBREAK` instruction with this option -set to 0. With IRQs enabled, an `SBREAK` normally triggers an IRQ 1. With -this option set to 0, an `SBREAK` will trap the processor without +The core will still trap on `EBREAK` instructions with this option +set to 0. With IRQs enabled, an `EBREAK` normally triggers an IRQ 1. With +this option set to 0, an `EBREAK` will trap the processor without triggering an interrupt. #### ENABLE_PCPI (default = 0) @@ -448,11 +448,11 @@ interrupt handler returns. The IRQs 0-2 can be triggered internally by the following built-in interrupt sources: -| IRQ | Interrupt Source | -| ---:| -----------------------------------| -| 0 | Timer Interrupt | -| 1 | SBREAK or Illegal Instruction | -| 2 | BUS Error (Unalign Memory Access) | +| IRQ | Interrupt Source | +| ---:| ------------------------------------| +| 0 | Timer Interrupt | +| 1 | EBREAK/ECALL or Illegal Instruction | +| 2 | BUS Error (Unalign Memory Access) | This interrupts can also be triggered by external sources, such as co-processors connected via PCPI. |