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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-06 21:27:07 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-06 21:27:07 +0200 |
| commit | 2107a328c4d1fe406791dc4c53ea49e246f0ef6c (patch) | |
| tree | 40151b6ccfe94cbe9e08f851b1be677588c5a4bc /dhrystone | |
| parent | bc8ffd2ecbd262e001ceb2c010375446fbdc5d3b (diff) | |
| download | picorv32-2107a328c4d1fe406791dc4c53ea49e246f0ef6c.tar.gz picorv32-2107a328c4d1fe406791dc4c53ea49e246f0ef6c.zip | |
Added insn timing hack to dryhstone testbench
Diffstat (limited to 'dhrystone')
| -rw-r--r-- | dhrystone/testbench.v | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index 216cc87..c14779e 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -43,12 +43,14 @@ module testbench; assign mem_ready = 1; always @(posedge clk) begin - mem_rdata <= memory[mem_la_addr >> 2]; + mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx; if (mem_valid) begin case (mem_addr) 32'h1000_0000: begin +`ifndef INSN_TIMING $write("%c", mem_wdata); $fflush(); +`endif end default: begin if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; @@ -72,4 +74,16 @@ module testbench; $finish; end end + +`ifdef INSN_TIMING + initial begin + repeat (100000) @(posedge clk); + $finish; + end + always @(uut.count_instr[0]) begin + // iverilog -DINSN_TIMING testbench.v ../picorv32.v && ./a.out > x + // sed 's,.*## ,,' x | gawk 'x != "" {print x,$2-y;} {x=$1;y=$2;}' | sort | uniq -c | sort -k3 -n + $display("## %-s %d", uut.instruction, uut.count_cycle); + end +`endif endmodule |