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| author | Clifford Wolf <clifford@clifford.at> | 2015-06-08 08:59:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-06-08 09:08:19 +0200 |
| commit | a9532f81edc0211e404f5c0cf4348bd55b6d9674 (patch) | |
| tree | 4dab90aa38358e04832966c585a8a900c545c925 /dhrystone | |
| parent | 32208c0b7096a36fac93e8c1074f283741ca5356 (diff) | |
| download | picorv32-a9532f81edc0211e404f5c0cf4348bd55b6d9674.tar.gz picorv32-a9532f81edc0211e404f5c0cf4348bd55b6d9674.zip | |
Refactored instruction decoder
Diffstat (limited to 'dhrystone')
| -rw-r--r-- | dhrystone/testbench.v | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index 9e0d329..c3c766d 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -50,8 +50,7 @@ module testbench; assign mem_ready = 1; always @(posedge clk) begin - if (mem_la_read) - mem_rdata <= memory[mem_la_addr >> 2]; + mem_rdata <= mem_la_read ? memory[mem_la_addr >> 2] : 'bx; if (mem_la_write) begin case (mem_la_addr) 32'h1000_0000: begin |