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author | Clifford Wolf <clifford@clifford.at> | 2016-08-30 11:16:19 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-08-30 11:16:19 +0200 |
commit | 2603ca492b75e81b93eedf1897fe794f2d621997 (patch) | |
tree | 5e778bc42cbf6e99e287f85f7a4d4d62194e404c /picorv32.v | |
parent | a6210c06d4c1fef1fb6e72aec7b87a88a6f2f8f4 (diff) | |
parent | bfba9b3eb34bfd9cc5d516153ddc960a44f7c5f2 (diff) | |
download | picorv32-2603ca492b75e81b93eedf1897fe794f2d621997.tar.gz picorv32-2603ca492b75e81b93eedf1897fe794f2d621997.zip |
Merged picorv32_pcpi_fast_mul changes
Diffstat (limited to 'picorv32.v')
-rw-r--r-- | picorv32.v | 12 |
1 files changed, 9 insertions, 3 deletions
@@ -1862,7 +1862,7 @@ module picorv32_pcpi_mul #( always @(posedge clk) begin pcpi_wr <= 0; pcpi_ready <= 0; - if (mul_finish) begin + if (mul_finish && resetn) begin pcpi_wr <= 1; pcpi_ready <= 1; pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; @@ -1889,7 +1889,8 @@ module picorv32_pcpi_fast_mul ( wire instr_rs2_signed = |{instr_mulh}; reg active1, active2, shift_out; - reg [63:0] rs1, rs2, rd; + reg [32:0] rs1, rs2; + reg [63:0] rd; always @* begin instr_mul = 0; @@ -1908,7 +1909,7 @@ module picorv32_pcpi_fast_mul ( end always @(posedge clk) begin - rd <= rs1 * rs2; + rd <= $signed(rs1) * $signed(rs2); end always @(posedge clk) begin @@ -1928,6 +1929,11 @@ module picorv32_pcpi_fast_mul ( end active2 <= active1; shift_out <= instr_any_mulh; + + if (!resetn) begin + active1 <= 0; + active2 <= 0; + end end assign pcpi_wr = active2; |