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| author | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-06-06 10:46:52 +0200 |
| commit | f4bb91b060211884fc0b85479fb6becf20daeb1f (patch) | |
| tree | d971e626fe57262b7830211644f043477b33c562 /picorv32.v | |
| parent | 490a7345191f9841fa953d18b27c8485171406ce (diff) | |
| download | picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.tar.gz picorv32-f4bb91b060211884fc0b85479fb6becf20daeb1f.zip | |
RISC-V ISA 2.1 now calls "sbreak" officially "ebreak"
Diffstat (limited to 'picorv32.v')
| -rw-r--r-- | picorv32.v | 30 |
1 files changed, 15 insertions, 15 deletions
@@ -97,7 +97,7 @@ module picorv32 #( output reg [31:0] eoi ); localparam integer irq_timer = 0; - localparam integer irq_sbreak = 1; + localparam integer irq_ebreak = 1; localparam integer irq_buserror = 2; localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; @@ -503,7 +503,7 @@ module picorv32 #( reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; - reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_scall_sbreak; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; wire instr_trap; @@ -919,7 +919,7 @@ module picorv32 #( instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; - instr_scall_sbreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; @@ -1273,11 +1273,11 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin pcpi_valid <= 0; - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1286,9 +1286,9 @@ module picorv32 #( cpu_state <= cpu_state_ld_rs2; end end else begin - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1423,11 +1423,11 @@ module picorv32 #( latched_store <= pcpi_int_wr; cpu_state <= cpu_state_fetch; end else - if (CATCH_ILLINSN && (pcpi_timeout || instr_scall_sbreak)) begin + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin pcpi_valid <= 0; - `debug($display("SBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) - if (ENABLE_IRQ && !irq_mask[irq_sbreak] && !irq_active) begin - next_irq_pending[irq_sbreak] = 1; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; cpu_state <= cpu_state_fetch; end else cpu_state <= cpu_state_trap; @@ -1574,7 +1574,7 @@ module picorv32 #( end else cpu_state <= cpu_state_trap; end - if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_scall_sbreak) begin + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin cpu_state <= cpu_state_trap; end |