Added osu018 yosys synthesis script

4 files changed, 97 insertions, 0 deletions

diff --git a/scripts/vivado/.gitignore b/scripts/vivado/.gitignore
new file mode 100644
index 0000000..74c116e
--- /dev/null
+++ b/scripts/vivado/.gitignore
@@ -0,0 +1,4 @@
+fsm_encoding.os
+synth_vivado.log
+synth_vivado_*.backup.log
+synth_vivado_syn.v
diff --git a/scripts/vivado/synth_vivado.tcl b/scripts/vivado/synth_vivado.tcl
new file mode 100644
index 0000000..386a070
--- /dev/null
+++ b/scripts/vivado/synth_vivado.tcl
@@ -0,0 +1,18 @@
+
+# vivado -nojournal -log synth_vivado.log -mode batch -source synth_vivado.tcl
+
+read_verilog synth_vivado_soc.v
+read_verilog ../../picorv32.v
+read_xdc synth_vivado.xdc
+
+synth_design -part xc7a15t-csg324 -top picorv32_axi
+# synth_design -part xc7a15t-csg324 -top test_soc
+opt_design
+place_design
+route_design
+
+report_utilization
+report_timing
+
+write_verilog -force synth_vivado_syn.v
+
diff --git a/scripts/vivado/synth_vivado.xdc b/scripts/vivado/synth_vivado.xdc
new file mode 100644
index 0000000..f2c7ea2
--- /dev/null
+++ b/scripts/vivado/synth_vivado.xdc
@@ -0,0 +1 @@
+create_clock -period 4.00 [get_ports clk]
diff --git a/scripts/vivado/synth_vivado_soc.v b/scripts/vivado/synth_vivado_soc.v
new file mode 100644
index 0000000..0b92d39
--- /dev/null
+++ b/scripts/vivado/synth_vivado_soc.v
@@ -0,0 +1,74 @@
+`timescale 1 ns / 1 ps
+
+module test_soc (
+	input         clk,
+	input         resetn,
+	output        trap,
+	output [7:0]  out_byte,
+	output reg    out_byte_en,
+
+	output        monitor_valid,
+	output [31:0] monitor_addr,
+	output [31:0] monitor_data
+);
+	parameter MEM_SIZE = 64*1024/4;
+
+	wire mem_valid;
+	wire mem_instr;
+	wire mem_ready;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [3:0] mem_wstrb;
+	reg [31:0] mem_rdata;
+
+	wire mem_la_read;
+	wire mem_la_write;
+	wire [31:0] mem_la_addr;
+	wire [31:0] mem_la_wdata;
+	wire [3:0] mem_la_wstrb;
+
+	picorv32 uut (
+		.clk         (clk         ),
+		.resetn      (resetn      ),
+		.trap        (trap        ),
+		.mem_valid   (mem_valid   ),
+		.mem_instr   (mem_instr   ),
+		.mem_ready   (mem_ready   ),
+		.mem_addr    (mem_addr    ),
+		.mem_wdata   (mem_wdata   ),
+		.mem_wstrb   (mem_wstrb   ),
+		.mem_rdata   (mem_rdata   ),
+		.mem_la_read (mem_la_read ),
+		.mem_la_write(mem_la_write),
+		.mem_la_addr (mem_la_addr ),
+		.mem_la_wdata(mem_la_wdata),
+		.mem_la_wstrb(mem_la_wstrb)
+	);
+
+	assign monitor_valid = mem_valid;
+	assign monitor_addr = mem_addr;
+	assign monitor_data = mem_wstrb ? mem_wdata : mem_rdata;
+
+	reg [31:0] memory [0:MEM_SIZE-1];
+	initial $readmemh("../firmware/firmware.hex", memory);
+
+	assign mem_ready = 1;
+	assign out_byte = mem_wdata[7:0];
+
+	always @(posedge clk) begin
+		out_byte_en <= 0;
+		if (mem_la_read)
+			mem_rdata <= memory[mem_la_addr >> 2];
+		else
+		if (mem_la_write && (mem_la_addr >> 2) < MEM_SIZE) begin
+			if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0];
+			if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8];
+			if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16];
+			if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24];
+		end
+		else
+		if (mem_la_write && mem_la_addr == 32'h1000_0000) begin
+			out_byte_en <= 1;
+		end
+	end
+endmodule