diff options
Diffstat (limited to 'dhrystone')
-rw-r--r-- | dhrystone/testbench.v | 45 |
1 files changed, 26 insertions, 19 deletions
diff --git a/dhrystone/testbench.v b/dhrystone/testbench.v index bfa9fbc..9e0d329 100644 --- a/dhrystone/testbench.v +++ b/dhrystone/testbench.v @@ -19,22 +19,29 @@ module testbench; wire [31:0] mem_wdata; wire [3:0] mem_wstrb; reg [31:0] mem_rdata; + wire mem_la_read; + wire mem_la_write; wire [31:0] mem_la_addr; + wire [31:0] mem_la_wdata; + wire [3:0] mem_la_wstrb; picorv32 uut ( - .clk (clk ), - .resetn (resetn ), - .trap (trap ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ), - .mem_la_read(mem_la_read), - .mem_la_addr(mem_la_addr) + .clk (clk ), + .resetn (resetn ), + .trap (trap ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ), + .mem_la_read (mem_la_read ), + .mem_la_write(mem_la_write), + .mem_la_addr (mem_la_addr ), + .mem_la_wdata(mem_la_wdata), + .mem_la_wstrb(mem_la_wstrb) ); reg [31:0] memory [0:64*1024/4-1]; @@ -45,19 +52,19 @@ module testbench; always @(posedge clk) begin if (mem_la_read) mem_rdata <= memory[mem_la_addr >> 2]; - if (mem_valid) begin - case (mem_addr) + if (mem_la_write) begin + case (mem_la_addr) 32'h1000_0000: begin `ifndef TIMING - $write("%c", mem_wdata); + $write("%c", mem_la_wdata); $fflush(); `endif end default: begin - if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0]; - if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8]; - if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16]; - if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24]; + if (mem_la_wstrb[0]) memory[mem_la_addr >> 2][ 7: 0] <= mem_la_wdata[ 7: 0]; + if (mem_la_wstrb[1]) memory[mem_la_addr >> 2][15: 8] <= mem_la_wdata[15: 8]; + if (mem_la_wstrb[2]) memory[mem_la_addr >> 2][23:16] <= mem_la_wdata[23:16]; + if (mem_la_wstrb[3]) memory[mem_la_addr >> 2][31:24] <= mem_la_wdata[31:24]; end endcase end |