| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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fix typo in picosoc/Makefile for hx8k board
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Use SPRAM on ICE40UP5K based boards
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Various touchups to scripts/icestorm demo
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With arachne-pnr this circuit couldn't hit 60MHz, just barely under it.
OTOH, nextpnr hits about ~68 MHz. So let's set it somewhere inbetween to
make sure this is true over time!
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Notes about how to build proper simulation vs hardware bitstreams.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This freestanding firmware doesn't need anything from the supporting
toolchain.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This makes it easier to build separate bitstreams for simulation targets
vs the real bitstream for hardware, without editing any source code.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This dumps a simple IceTime report for the bitstream; we fix the device
package to CT256, corresponding to the HX8K.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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The IceStorm example core doesn't include compressed instructions or the
MULT extension; it is an rv32i core, not rv32i[m|c]. If the given
riscv32 toolchain is not explicitly told to generate rv32i code for the
firmware, it may generate invalid instructions which cause a trap during
simulation or on the hardware itself (although CATCH_ILLINSN is set to
zero in this case, too).
Luckily, any rv32i* toolchain (rv32imc for example) can fit the bill
here -- there's no use of libgcc or anything (which might introduce
illegal instructions generated previously) so just forcing the compiler
to generate the right code works nicely.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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nextpnr-ice40 gives a better fMAX for this design (by about ~9Mhz for
me: ~59MHz -> ~68MHz) and is The Way Of The Future.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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This touches up the Makefile so that it:
- uses $@, $< and $^ in more places for brevity and robustness (typo
guards, etc)
- tracks dependencies slightly better (e.g. .pcf file changes weren't
tracked before)
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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The net result of this is that cd'ing into the main source directory and
running:
$ nix-shell
will get you every tool needed to immediately do RISC-V development with
picorv32 or picosoc (assuming you're targeting ICE40 or ECP5).
The shell.nix file contains many comments on how to use the resulting
environment.
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Signed-off-by: Austin Seipp <aseipp@pobox.com>
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Added echo command to PicoSoc firmware for testing UART
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Add readme file for torture test
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Icebreaker example
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Update vivado scripts
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Alignment fix for global symbols fixes #97
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Added new testbench and linker file for ROM load
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Fix typo in README.md
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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closes #88
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Fix PicoSoC firmware filename for simulation
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Update Risc-V website link for tools
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Current link ends up in 404 error
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Add FuseSoC support for icebreaker
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