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author | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-10-07 13:43:16 +0100 |
commit | f9ca386bda2fe89287b9bb65d3d28e0c150d8984 (patch) | |
tree | c7ad596237f3d63829d7a7574a93f220a9fc721d /presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys | |
download | fpga20_fubfst-f9ca386bda2fe89287b9bb65d3d28e0c150d8984.tar.gz fpga20_fubfst-f9ca386bda2fe89287b9bb65d3d28e0c150d8984.zip |
Diffstat (limited to 'presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys')
-rw-r--r-- | presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v new file mode 100644 index 0000000..0700c08 --- /dev/null +++ b/presentation/ExampleRun/output2/fuzz_1/equiv_identity_yosys/top.v @@ -0,0 +1,8 @@ +module top (y_1, y_2, clk, wire0, wire1, wire2, wire3); + top_gen top_gen (.y(y_1), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3)); + top_syn top_syn (.y(y_2), .clk(clk), .wire0(wire0), .wire1(wire1), .wire2(wire2), .wire3(wire3)); + always + @(posedge clk) begin + assert ((y_1 == y_2)); + end +endmodule |