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author | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 18:43:11 +0100 |
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committer | Yann Herklotz <git@yannherklotz.com> | 2021-09-10 18:43:11 +0100 |
commit | 3fb145c8ff5d539b8a2891714834420d275dece4 (patch) | |
tree | cfdff401e7e7a34c62394f12dc02557e866b4dc5 /verilog.tex | |
parent | 4d019a44c0fc9d78dd498d4775d904f6a846d29f (diff) | |
download | oopsla21_fvhls-3fb145c8ff5d539b8a2891714834420d275dece4.tar.gz oopsla21_fvhls-3fb145c8ff5d539b8a2891714834420d275dece4.zip |
Revert the memory model drawing
Diffstat (limited to 'verilog.tex')
-rw-r--r-- | verilog.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/verilog.tex b/verilog.tex index b0af602..50d7640 100644 --- a/verilog.tex +++ b/verilog.tex @@ -130,8 +130,8 @@ The Verilog semantics do not define a memory model for Verilog, as this is not n \begin{figure} \centering \begin{tikzpicture} - \fill[compcertmemmodel,rounded corners=3pt] (0,0) rectangle (5,-4.3); - \fill[vericertmemmodel,rounded corners=3pt] (7,0) rectangle (12,-4.3); + \fill[compcertmemmodel,rounded corners=3pt] (0,0) rectangle (5,-5); + \fill[vericertmemmodel,rounded corners=3pt] (7,0) rectangle (12,-5); \node[right] at (0,-0.3) {\small \textbf{\compcert{}'s Memory Model}}; \node[right] at (7,-0.3) {\small \textbf{Verilog Memory Representation}}; \node[right] (x0) at (0.2,-1.9) {\small 0}; |