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BranchCommit messageAuthorAge
dev/schedulingStart working on supporting different back endsYann Herklotz2 years
masterFix some of the testing in MakefileYann Herklotz3 years
dev-michalisFix renamer skipping ram_memMichalis Pardalos3 years
oopsla21Use main instead of top for synthesising Vericert designsYann Herklotz3 years
dev/divAdd the dividerYann Herklotz3 years
exp/inl-cse-constSwitch CSE and const-propYann Herklotz3 years
dev/ioAdd predicate semantics to abstractYann Herklotz3 years
dev/dividerGet some Verilog output with dividersYann Herklotz3 years
dev/cond-const-propAdd parallel blockYann Herklotz3 years
michalis-mergeMerge branch 'master' into michalis-mergeYann Herklotz3 years
[...]
 
TagDownloadAuthorAge
v1.2.2vericert-kvx-1.2.2.tar.gz  vericert-kvx-1.2.2.zip  Yann Herklotz3 years
v1.2.1vericert-kvx-1.2.1.tar.gz  vericert-kvx-1.2.1.zip  Yann Herklotz3 years
v1.2.0vericert-kvx-1.2.0.tar.gz  vericert-kvx-1.2.0.zip  Yann Herklotz3 years
v1.1.0vericert-kvx-1.1.0.tar.gz  vericert-kvx-1.1.0.zip  Yann Herklotz3 years
v1.0.1vericert-kvx-1.0.1.tar.gz  vericert-kvx-1.0.1.zip  Yann Herklotz4 years
v1.0.0vericert-kvx-1.0.0.tar.gz  vericert-kvx-1.0.0.zip  Yann Herklotz4 years
v0.1.0vericert-kvx-0.1.0.tar.gz  vericert-kvx-0.1.0.zip  Yann Herklotz4 years
 
AgeCommit messageAuthorFilesLines
2022-03-14Start working on supporting different back endsdev/schedulingYann Herklotz3-32/+5
2022-03-13Add compilation flag for superblock schedulingYann Herklotz8-5/+18
2022-03-10Changes to make compilation passYann Herklotz14-175/+167
2022-03-10Remove CompCertYann Herklotz2-4/+0
2022-03-10Remove from .gitmodulesYann Herklotz2-4/+1
2022-03-10Try and define a translation from RTL to SRTLYann Herklotz6-9/+78
2022-03-10Add superblock scheduling backendYann Herklotz4-2/+9
2022-03-07Start work on reverse if-conversionYann Herklotz2-1/+84
2022-03-06Fix RAW dependency calculation for predicatesYann Herklotz1-0/+3
2022-03-05Update links in READMEYann Herklotz2-8/+8
[...]
 
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